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EM77950 bb controller product specification d oc . v ersion 1.0 elan microelectronics corp. october 2007
trademark acknowledgments: ibm is a registered trademark an d ps/2 is a trademark of ibm. windows is a trademark of microsoft corporation. elan and elan logo are trademarks of elan mi croelectronics corporation. copyright ? 2007 by elan microelectronics corporation all rights reserved printed in taiwan the contents of this specification are subject to change without further notice. elan microelectronics assumes no responsibility concerning the accuracy, adequacy, or comple teness of this specification. elan microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. such information and material may change to conform to each confirmed order. in no event shall elan microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. elan microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. the software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. elan microelectronics products are not intended for use in life support appliances, devices, or systems. use of elan microelectronics product in such applications is not supported and is prohibited. no part of this specification may be repr oduced or transmitted in any form or by any means without the expressed written permission of elan microelectronics. elan microelectronics corporation headquarters: no. 12, innovation road 1 hsinchu science park hsinchu, taiwan 308 tel : +886 3 563-9977 fax : +886 3 563-9966 http : //www.emc.com.tw hong kong: elan (hk) microelectronics corporation, ltd. flat a, 19f., world tech centre 95 how ming street, kwun tong kowloon, hong kong tel : +852 2723-3376 fax : +852 2723-7780 elanhk@emc.com.hk usa: elan information technology group (usa) p.o. box 601 cupertino, ca 95015 usa tel : +1 408 366-8225 fax : +1 408 366-8225 shenzhen: elan microelectronics shenzhen, ltd. 3f, ssmec bldg., gaoxin s . ave . i shenzhen hi-tech industrial park (south area), shenzhen china 518057 tel : +86 755 2601-0565 fax : +86 755 2601-0500 shanghai: elan microelectronics shanghai, ltd. #23, zone 115, lane 572, bibo rd. zhangjiang hi-tech park shanghai, china 201203 tel : +86 21 5080-3866 fax : +86 21 5080-4600
contents product specification (v1.0) 10.09.2007 ? iii contents 1 general description ................................................................................................ 1 2 features ................................................................................................................... 1 2.1 core.................................................................................................................. 1 2.2 oscillators/system clocks ................................................................................ 2 2.3 input and output (i/o) pins ............................................................................... 2 2.4 timers and counters ........................................................................................ 2 2.5 interrupt sources and features ........................................................................ 2 2.6 baseband (bb) ................................................................................................. 3 2.7 serial peripheral interface (spi) ....................................................................... 3 2.8 pulse width modulation (pwm) ........................................................................ 3 2.9 analog to digital converter (adc) .................................................................... 3 3 pins assignment ..................................................................................................... 4 4 pin description ........................................................................................................ 6 5 block diagram ......................................................................................................... 9 6 memory .................................................................................................................. 10 6.1 program memory ............................................................................................ 10 6.2 ram?register ................................................................................................ 11 7 function description............................................................................................. 25 7.1 special purpose registers.............................................................................. 25 7.1.1 accumulator ? acc ......................................................................................... 25 7.1.2 indirect addressing contents ? iac0 and iac1 ............................................... 25 7.1.3 high byte program counter hpc and low byte program counter lpc ......... 25 7.1.4 status register ? sr ....................................................................................... 26 7.1.5 ram bank selector ? rambs0 and rambs1 ................................................ 26 7.1.6 rom page selector ? romps ....................................................................... 27 7.1.7 indirect addressing pointers ? iap0 and iap1 ................................................ 27 7.1.8 indirect address pointer direction control register ? iapdr.......................... 27 7.1.9 table look-up pointer ? ltbl and htbl ........................................................ 28 7.1.10 stack pointer ? stkptr ................................................................................. 28 7.1.11 repeat counter ? rptc ................................................................................. 28 7.1.12 prescaler counter ? prc................................................................................ 28 7.1.13 real time clock counter ? rtcc................................................................... 28 7.1.14 interrupt flag register ? intf......................................................................... 28 7.1.15 key wake-up flag register ? kwuaif & kwubif......................................... 29 7.1.16 i/o port registers ? pta ~ ptf....................................................................... 29 7.1.17 16-bit free run counter (frc) ? lfrc hfrc & lfrcb ............................... 29 7.1.18 serial peripheral interface read register ? spirb......................................... 29 7.1.19 serial peripheral interface write register ? spiwb ........................................ 29
contents iv ? product specification (v1.0) 10.09.2007 7.1.20 adc converting value ? addata................................................................... 29 7.1.21 pwm duty ? dt0l/dt0h & dt1l/dt1h......................................................... 29 7.1.22 pwm period ? prd0l/prd0h & prd1l/prd1h........................................... 29 7.1.23 pwm duty latch ? dl0l/dl0h & dl1l/dl1h ................................................ 30 7.1.24 bb address register ? rfaar ....................................................................... 30 7.1.25 bb data buffer register ? rfdb..................................................................... 30 7.1.26 bb data read/write control register ? rfacr ............................................. 30 7.1.27 bb interrupt flag register ? rfintf .............................................................. 30 7.2 dual port register .......................................................................................... 31 7.3 system status, control and configuration registers....................................... 31 7.3.1 peripherals enable control ? prie ................................................................. 31 7.3.2 interrupts enable control ? inte .................................................................... 31 7.3.3 key wake-up enable control ? kwuaie & kwubie ...................................... 32 7.3.4 external interrupts edge control ? einted .................................................... 32 7.3.5 serial peripheral serial (spi) enable control register ? spic........................ 33 7.3.6 i/o control registers ? ioca~iocf................................................................ 33 7.3.7 pull-up resistance control registers for ports a~f ? puca~pucf............... 34 7.3.8 open drain control registers of port b/port c ? odcb/odcc ...................... 34 7.3.9 timer clock counter controller ? tccc ......................................................... 34 7.3.10 free run counter controller ? frcc ............................................................. 35 7.3.11 watchdog timer controller ? wdtc ............................................................... 35 7.3.12 adc analog input pin select ? adcais ......................................................... 36 7.3.13 adc configuration register ? adccr............................................................ 36 7.3.14 pwm control register ? pwmcr ................................................................... 37 7.3.15 bb interrupt control register ? rfinte.......................................................... 37 7.4 code option (rom-0x2fff)........................................................................... 38 8 baseband (bb)....................................................................................................... 39 8.1 bb: standard interface for the rfw102 series ............................................... 39 8.1.1 features .......................................................................................................... 39 8.1.2 description ...................................................................................................... 39 8.1.3 i/o and package description........................................................................... 40 8.1.4 bb architecture ............................................................................................... 42 8.2 bb description ................................................................................................ 42 8.2.1 reset............................................................................................................... 42 8.2.2 power saving modes ...................................................................................... 42 8.2.2.1 power-down mode ........................................................................... 42 8.2.2.2 idle mode.......................................................................................... 43 8.2.3 preamble correlation ...................................................................................... 43 8.2.4 refresh bit ...................................................................................................... 44 8.2.5 bit structure..................................................................................................... 44 8.2.6 crc ................................................................................................................ 45
contents product specification (v1.0) 10.09.2007 ? v 8.2.7 rx fifo .......................................................................................................... 46 8.2.8 tx fifo .......................................................................................................... 47 8.2.9 interrupt driver ................................................................................................ 47 8.2.10 packet size ..................................................................................................... 49 8.2.11 net_id and node_id filters ......................................................................... 49 8.2.12 carrier-sense.................................................................................................. 50 8.2.12.1 rfwaves carrier-sense algorithm ................................................... 50 8.2.13 receiver reference capacitor discharge ....................................................... 51 8.2.14 changing bb configuration ............................................................................. 52 8.2.15 input synchronizer .......................................................................................... 52 8.3 register description ....................................................................................... 52 8.3.1 bit length register (blr) ............................................................................... 53 8.3.2 preamble low register (pre-l) ..................................................................... 53 8.3.3 preamble high register (pre-h).................................................................... 53 8.3.4 packet parameter register (ppr)................................................................... 53 8.3.5 system control register1 (scr1)................................................................... 55 8.3.6 system control register 2 (scr2).................................................................. 55 8.3.7 system control register 3 (scr3).................................................................. 57 8.3.8 system control register 4 (scr4)................................................................. 58 8.3.9 transmit fifo status register (tfsr)............................................................ 59 8.3.10 receive fifo status register (rfsr) ............................................................ 59 8.3.11 location control register (lcr) ..................................................................... 59 8.3.12 node identity register (bir)............................................................................ 60 8.3.13 net identity register (nir) .............................................................................. 60 8.3.14 system status register (ssr) ........................................................................ 61 8.3.15 packet size register (psr) ............................................................................ 62 8.3.16 carrier sense register (csr) ......................................................................... 62 8.4 interrupt registers .......................................................................................... 63 8.4.1 interrupt enable register (ier) ....................................................................... 63 8.4.2 interrupt identification register (iir)................................................................ 64 8.5 list of bb register mapping............................................................................ 65 8.6 mcu bb control registers ............................................................................. 65 8.6.1 control registers list ...................................................................................... 65 8.6.2 bb control example ........................................................................................ 66 9 direction serial peripheral interface (spi) ........................................................... 68 9.1 introduction..................................................................................................... 68 9.2 features ......................................................................................................... 68 9.3 block diagram ................................................................................................ 68 9.4 transceiver timing.......................................................................................... 69 9.5 related registers with spi ............................................................................. 69
contents vi ? product specification (v1.0) 10.09.2007 9.6 function description ....................................................................................... 70 9.6.1 block diagram description .............................................................................. 70 9.6.2 signal & pin description.................................................................................. 70 10 analog to digital converter (adc)....................................................................... 71 10.1 adc control registers.................................................................................... 72 10.2 programming steps/considerations................................................................ 74 11 dual pulse width modulations (pwm0 and pwm1)............................................. 75 11.1 overview......................................................................................................... 75 11.2 pwm control registers .................................................................................. 76 11.3 pwm programming procedures/steps.... ........................................................ 78 12 interrupts................................................................................................................ 78 12.1 introduction..................................................................................................... 78 13 circuitry of input and output pins ....................................................................... 80 13.1 introduction..................................................................................................... 80 14 timer/counter system .......................................................................................... 80 14.1 introduction..................................................................................................... 80 14.2 time clock counter (tcc).............................................................................. 80 14.2.1 block diagram of tcc..................................................................................... 80 14.2.2 tcc control registers .................................................................................... 81 14.2.3 tcc programming procedures/steps ............................................................. 81 14.3 free run counter ........................................................................................... 82 14.3.1 block diagram of frc..................................................................................... 82 14.3.2 frc control registers .................................................................................... 82 14.3.3 frc programming procedures/steps ............................................................. 83 15 reset and wake up................................................................................................ 83 15.1 reset .............................................................................................................. 83 15.2 the status of rst, t, and p of the status register...................................... 83 15.3 system set-up time (sst) ............................................................................. 84 15.4 wake-up procedure on power-on reset......................................................... 85 16 oscillators.............................................................................................................. 85 16.1 introduction..................................................................................................... 85 16.2 clock signal distribution ................................................................................. 85 16.3 pll oscillator ................................................................................................. 86 16.4 selected pll oscillation out ........................................................................... 86 17 low-power mode ................................................................................................... 86 17.1 introduction..................................................................................................... 86 17.2 green mode.................................................................................................... 87 17.3 sleep mode .................................................................................................... 87
contents product specification (v1.0) 10.09.2007 ? vii 18 instruction description ......................................................................................... 88 18.1 instruction set summary................................................................................. 88 19 electrical specification ......................................................................................... 90 19.1 absolute maximum ratings ............................................................................ 90 19.2 dc electrical characteristic ............................................................................ 90 19.3 voltage detector electrical characteristic ....................................................... 91 19.4 ac electrical characteristic............................................................................. 91 19.4.1 mcu................................................................................................................ 91 19.4.2 bb ................................................................................................................... 92 20 application circuit................................................................................................. 93 appendix a package type......................................................................................................... 94 b package information ............................................................................................. 94 specification revision history doc. version revision description date 1.0 initial released version 2007/10/09
contents viii ? product specification (v1.0) 10.09.2007
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 1 (this specification is subject to change without further notice) 1 general description the EM77950 from elan electronics is a low-cost and high performance 8-bit cmos advance risc architecture microcontroller device. it has an on-chip 1-mbps rf driver module/base band (bb), serial peripheral interface (spi), dual pulse width modulation (pwm) with 16-bit resolution, an 8-bit timer clock counter (tcc) and a 16-bit free run timer, multi-channel analog to digital converter (adc) with 8-bit resolution, key wake-up function (kwu), power-on reset (por), watchdog timer (wdt), and power saving sleep mode. all these features combine to ensure applications require the least external components, hence, not only reduce system cost, but also have the advantage of low power consumption and enhanced device reliability. the 52-pin EM77950 is available in a very cost-effective version that provides a single chip solution in designing wireless products. 2 features 2.1 core ? operating voltage range: 2.2v ~ 3.6v dc (adc reference volt 3v) ? operating temperature range: 0 c ~ 70 c ? operating frequency range: dc ~ 48mhz (1 clock/cycle) ? 6mhz external clock source ? 6/12/24/48 mhz to core clock ? 6/12/24/48 mhz to clock ? internal memory ? 12k x 16 bits of on-chip program rom ? 896 x 8 bits of on-chip register (sram) ? watchdog timer (wdt) ? 32 level stacks for both call and interrupt subroutine ? internal power-on reset (por) function ? code protection function available ? all single cycle (1 clock) instruction except for conditional branches which are two or three cycles. ? direct, indirect and relative addressing modes ? low power, high speed cmos technology
EM77950 bb controller 2 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) ? power consumption: < 4 ma @ 3.3v, 6 mhz < 60 a @ 3.0v, (rc = 32.768 khz) < 1 a standby current ? 52/44-pin qfp package 2.2 oscillators/system clocks ? three oscillator options: ? crystal/resonate oscillator of high frequency ? pll oscillator: 6mhz, 12 mhz, 24 mhz, and 48 mhz (external crystal should be 6 mhz) ? external rc oscillator ? three modes of system clocks: ? sleep mode ? green mode ? normal mode ? internal rc oscillator for power-on reset (por) and watchdog timer (wdt) 2.3 input and output (i/o) pins ? 40 i/o pins max. ? pull-up resistor options ? key wake-up function ? open drain output options 2.4 timers and counters ? programmable 8-bit real time clock/counter (tcc) with prescaler and overflow interrupt ? 16-bit free run counter (frc) with overflow interrupt 2.5 interrupt sources and features ? hardware priority check ? different interrupt vectors ? interrupts ? key wake-up function ? external pin interrupt ? 16-bit free run counter overflow ? tcc (time-base) overflow; ? read buffer full interrupt in serial peripheral interface (spi) ? an analog to digital converting (adc) complete ? one period of pulse width modulation (pwm) complete
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 3 (this specification is subject to change without further notice) ? base band (bb) function interrupts: ? csd: carrier sense detection ? tx_ae: tx_fifo almost full ? rx_af: rx_fifo almost full ? tx_ empty: finish a transmitting a package ? rx_of: rx_fifo overflow ? link_dis: zero counter capacitor discharge mechanism ? lock_out: finish receiving a package ? lock_in: start receiving a package 2.6 baseband (bb) ? serial to parallel conversion of rfw102 interface ? parallel interface to rfw102 modem ? serial to parallel conversion of rfw102 interface ? input fifo (rx_fifo) ? output fifo (tx_fifo) ? preamble correlation ? packet address filter (network and unique) ? crc calculation ? inter-rfwaves networks carrier-sense ? discharge of rfw-102 reference capacitor ? compensate for clock drifts between the transmitting EM77950 and the receiving EM77950 up to 1000ppm. hence, the EM77950 requires low performance crystal. ? interrupt driver ? connected to the EM77950?s internal interrupt and informs the EM77950 about bb events. 2.7 serial peripheral interface (spi) ? either msb or lbs can be transmitted/received first ? both master and slave modes available 2.8 pulse width modulation (pwm) ? dual pulse width modulation (pwm) with 16-bit resolution 2.9 analog to digital converter (adc) ? 16 multi-channel analog to digital converter with 8-bit resolution
EM77950 bb controller 4 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 3 pins assignment avdd 1 2 3 4 dvdd pa0/kwu8 5 6 7 8 /rst 9 10 11 pd2/adc2 37 36 35 osci 34 osco1 33 plcc 32 31 30 29 28 27 pa1/kwu9 pa2/kwua pa3/kwub pa4 pa5 pa6 pd1/adc1 pd0/adc0 pc5/pwm1 pc4/int1 pc3/int0 pc2/sck pc1/sd0 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 pa7/pwm0 pb0/kwu0 pb1/kwu1 pb2/kwu2 pb3/kwu3 pb4/kwu4 pb5/kwu5 pb6/kwu6 pb7/kwu7 rf_act txrx rfio dvss pc0/sdi pf1 avss pf0/osco2 pe7/adcf pe6/adce pe5/adcd pe4/adcc pe3/adcb pe2/adca pe1/adc9 pe0/adc8 vref pd7/adc7 pd6/adc6 pd5/adc5 pd4/adc4 pd3/adc3 12 13 38 39 EM77950a fig. 3-1 pin configuration of EM77950a
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 5 (this specification is subject to change without further notice) EM77950b avdd 1 2 3 4 dvdd pa0/kwu8 5 6 7 8 /rst 9 10 11 pd2/adc2 33 32 31 osci 30 osco1 29 plcc 28 27 26 25 24 23 pa1/kwu9 pa2/kwua pa3/kwub pa4 pa5 pa6 pd1/adc1 pd0/adc0 pc5/pwm1 pc4/int1 pc3/int0 pc2/sck pc1/sd0 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 pa7/pwm0 pb0/kwu0 pb1/kwu1 pb2/kwu2 pb3/kwu3 rf_act txrx rfio dvss pc0/sdi pf1 avss pf0/osco2 pe3/adcb pe2/adca pe1/adc9 pe0/adc8 vref pd7/adc7 pd6/adc6 pd5/adc5 pd4/adc4 pd3/adc3 fig. 3-2 pins configuration of EM77950b
EM77950 bb controller 6 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 4 pin description the table below shows the corresponding relationship between the pad and pins of EM77950a pin # symbol type schmitt trigger pull high /50k open drain function description 1 ptf0/osco2 i/o ? ? pin 0 of port f selected pll clock out 2 pf1 i/o ? ? pin 1 of port f 3~6 kwu8~b, pa0~3 i/o ? ? pins 0~3 of port a (default). key wake-up 8~b 7 /rst ? ? ? reset pin 8~10 pta4~6 i/o ? ? pins 4~6 of port a. 11 pwm0/pta7 i/o ? ? pin 7 of port a. pwm0 output 12~19 pb0 ~ pb7 i/o ? pins 0~7 of port b (default). key wake-up 0~7 20 dvdd ? ? ? ? power supply for digital circuit. the power source value should be within the range of the operating voltage. 21 rf_act o ? ? ? bb/rf active 22 txrx o ? ? ? transceiver modes control 23 rfio i/o ? ? ? transceiver to/from rf modem 24 dvss ? ? ? ? ground pin for digital circuit 25 sdi/ptc0 i/o data in of spi pin 0 of port c 26 sdo/ptc1 i/o data out of spi pin 1 of port c 27 sck/ptc2 i/o clock of spi pin 2 of port c 28 eint0/ ptc3 i/o ? external interrupt pin 0 pin 3 of port c 29 eint1/ ptc4 i/o ? external interrupt pin 1 pin 4 of port c 30 pwm1/ptc5 i/o ? pin 5 of port c. pwm1 output 31 pllc ? ? ? ? external capacitor for pll circuit 32 osco1 o ? ? ? output of crystal oscillator 33 osci i ? ? ? input of crystal oscillator 34 avss ? ? ? ? ground pin for analog circuit
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 7 (this specification is subject to change without further notice) pin # symbol type schmitt trigger pull high /50k open drain function description 35~42 ptd0~7, adc0~7 i/o ? ? pins 0~7 of port d inputs 0~7 of adc 43 vref i ? ? ? reference voltage for adc 44~51 pte0~7, adc8~f i/o ? ? pins 0~7 of port e inputs 8~f of adc 52 avdd ? ? ? ? power supply for analog circuit. the power source value should be within the range of the operating voltage. the table below shows the corresponding relationship between the pad and pins of EM77950b pin # symbol type schmitt trigger pull high /50k open drain function description 1 ptf0/osco2 i/o ? ? pin 0 of port f selected pll clock out 2 pf1 i/o ? ? pin 1 of port f 3~6 kwu8~b, pa0~3 i/o ? ? pins 0~3 of port a (default) key wake-up 8~b 7 /rst ? ? ? reset pin 8~10 pta4~6 i/o ? ? pins 4~6 of port a 11 pwm0/pta7 i/o ? ? pin 7 of port a. pwm0 output 12~15 pb0 ~ pb3 i/o ? pins 0~3 of port b (default) key wake-up 0~7 16 dvdd ? ? ? ? power supply for digital circuit. the power source value should be within the range of the operating voltage. 17 rf_act o ? ? ? bb/rf active 18 txrx o ? ? ? transceiver modes control 19 rfio i/o ? ? ? transceiver to/from rf modem 20 dvss ? ? ? ? ground pin for digital circuit 21 sdi/ptc0 i/o data in of spi pin 0 of port c 22 sdo/ptc1 i/o data out of spi pin 1 of port c
EM77950 bb controller 8 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) pin # symbol type schmitt trigger pull high /50k open drain function description 23 sck/ptc2 i/o clock of spi pin 2 of port c 24 eint0/ ptc3 i/o ? external interrupt pin 0 pin 3 of port c 25 eint1/ ptc4 i/o ? external interrupt pin 1 pin 4 of port c 26 pwm1/ptc5 i/o ? pin 5 of port c pwm1 output 27 pllc ? ? ? ? external capacitor for pll circuit 28 osco1 o ? ? ? output of crystal oscillator 29 osci i ? ? ? input of crystal oscillator 31~38 ptd0~7, adc0~7 i/o ? ? pins 0~7 of port d inputs 0~7 of adc 39 vref i ? ? ? reference voltage for adc 40~43 pte0~3, adc8~b i/o ? ? pins 0~3 of port e inputs 8~b of adc 44 avdd ? ? ? ? power supply for analog circuit. the power source value should be within the range of the operating voltage.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 9 (this specification is subject to change without further notice) 5 block diagram pll osc wat chdog controller lx osc cpu frc tcc internal rc osc. wdtce adc osci osco1 green sleep base band m u x 1 0 m u x spi wmoscs0 wmoscs1 6/12/24 mhz oscs0 oscs1 plldiv ppscl0 ppscl1 ppscl2 osc02
EM77950 bb controller 10 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 6 memory 6.1 program memory the EM77950 has a 14-bit program counter (pc). the space of program memory, which is partitioned into 2 pages can address up to 12k. one page has 8k in length, and the other is 4k. fig. 6-1 depicts the profile of the program memory and stack. the initial address is 0x0000. the table of interrupt-vectors starts from 0x10 to 0x80 with every other eight-address space. a13 a12 a11 a10 a7~a0 a9 a8 stack 0 stack 1 stack 1e stack 1f call ret retl reti ps0 address page 0 0000 ~ 1 fff 0 hpc lpc addr vector 0000 reset 0010 key wake-up 0020 tccof 0028 frcof acc2 acc1 acc0 sr2 sr1 sr0 rambs02 rambs01 rambs00 1 2000 ~ 2fff 1 romps2 romps1 romps0 int fig. 6-1 configuration of program memory (rom) for EM77950
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 11 (this specification is subject to change without further notice) 6.2 ram?register a total of 896 accessible bytes of data memory are available for the EM77950. by function, they are classified into general purpose registers, system control/configuration registers, specific purpose registers, baseband (bb) control/status registers, spi control/status registers, timer/counter registers, and io port status/control registers. all of the mentioned registers except i/o po rts and their related control registers are implemented as static ram. the ram configurations are shown in fig. 6-2. 00 30 system, configuration, clock, io port registers general purpose registers 31 3f dual port register 40 7f peripherals, and interrupts control registers 80 9a 9b ff general purpose registers of bank 0 general purpose registers of bank 2 2ff 280 general purpose registers of bank 3 3ff 380 general purpose registers of bank 4 4ff 480 general purpose registers of bank 5 5ff 580 000 010 011 100 101 general purpose registers of bank 6 6ff 680 110 fig. 6-2 of data memory (ram) configuration
EM77950 bb controller 12 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) the table is a summary of all registers except general purpose registers. addr name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 full name indirect addressing register contents bit name iac07 iac06 iac05 iac04 iac03 iac02 iac01 iac00 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x00 iac0 wake-up from int p p p p p p p p full name most significant byte of programming counter bit name pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 read / write (r/w) r r r r r r r r power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x01 hpc wake-up from int jump to corresponding interrupt vector or continue to execute next instruction full name least significant byte of programming counter bit name pcf pce pcd pcc pcb pca pc9 pc8 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x02 lpc wake-up from int jump to corresponding interrupt vector or continue to execute next instruction full name status register bit name - - rst t p z dc c read / write (r/w) - - r/w r/w r/w r/w r/w r/w power-on - - 0 1 1 u u u /reset and wdt - - p t t p p p 0x03 sr wake-up from int - - p t t p p p full name ram bank selector 0 bit name - - - - - rbs02 rbs01 rbs00 read / write (r/w) - - - - - r r r power-on - - - - - 0 0 0 /reset and wdt - - - - - 0 0 0 0x04 rambs 0 wake-up from int - - - - - p p p full name rom page selector bit name - - - - - - - rps0 read / write (r/w) - - - - - - - r/w power-on - - - - - - - 0 /reset and wdt - - - - - - - 0 0x05 romps wake-up from int - - - - - - - p
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 13 (this specification is subject to change without further notice) addr name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 full name indirect addressing pointer 0 bit name iap07 iap06 iap05 iap04 iap03 iap02 iap01 iap00 read / write ( r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x06 iap0 wake-up from int p p p p p p p p full name ram bank selector 1 bit name - - - - - rbs12 rbs11 rbs10 read / write ( r/w) - - - - - r/w r/w r/w power-on - - - - - 0 0 0 /reset and wdt - - - - - 0 0 0 0x07 rambs1 wake-up from int - - - - - p p p full name indirect addressing pointer 1 bit name iap17 iap16 iap15 iap14 iap13 iap12 iap11 iap10 read / write ( r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x08 iap1 wake-up from int p p p p p p p p full name indirect addressing contents 1 bit name iac17 iac16 iac15 iac14 iac13 iac12 iac11 iac10 read / write ( r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x09 iac1 wake-up from int p p p p p p p p full name indirect address pointer direction control register bit name - - - - iap1_d iap0_d iap1_d_e iap0_d_e read / write ( r/w) - - - - r/w r/w r/w r/w power-on - - - - 0 0 0 0 /reset and wdt - - - - 0 0 0 0 0x0a iapdr wake-up from int - - - - p p p p full name least significant byte of table look-up bit name tbl7 tbl6 tbl5 tbl4 tbl3 tbl2 tbl1 tbl0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x0b ltbl wake-up from int p p p p p p p p
EM77950 bb controller 14 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) addr name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 full name most significant byte of table look-up bit name tblf tble tbld tblc tblb tbla tbl9 tbl8 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x0c htbl wake-up from int p p p p p p p p full name stack pointer bit name stkpt7 stkpt6 stkpt5 stkpt4 stkpt3 stkpt2 stkpt1 stkpt0 read / write (r/w) r r r r r r r r power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 0x0d stkptr wake-up from int p p p p p p p p full name repeat pointer bit name rptc7 rptc6 rptc5 rptc4 rptc3 rptc2 rptc1 rptc0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x0e rptc wake-up from int p p p p p p p p full name prescaler counter bit name prc7 prc6 prc5 prc4 prc3 prc2 prc1 prc0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x0f prc wake-up from int 0 0 0 0 0 0 0 0 full name time clock/counter bit name tcc7 tcc6 tcc5 tcc4 tcc3 tcc2 tcc1 tcc0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x10 tcc wake-up from int 0 0 0 0 0 0 0 0 full name interrupt flag bit name adif rbfif pwm1if pwm0if eint1f eint0f tccof frcof read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x11 intf wake-up from int p p p p p p p p
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 15 (this specification is subject to change without further notice) addr name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 full name port a key wake up interrupt flag bit name - - - - kwubif kwuaif kwu9if kwu8if read / write (r/w) - - - - r/w r/w r/w r/w power-on - - - - 0 0 0 0 /reset and wdt - - - - 0 0 0 0 0x12 kwuaif wake-up from int - - - - p p p p full name port b key wake up interrupt flag bit name kwu7if kwu6if kwu5if kwu4if kwu3if kwu2if kwu1if kwu0if read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x13 kwubif wake-up from int p p p p p p p p full name general purpose i/o port, port a bit name pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on u u u u u u u u /reset and wdt u u u u u u u u 0x14 pta wake-up from int p p p p p p p p full name general purpose i/o port, port b bit name ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on u u u u u u u u /reset and wdt u u u u u u u u 0x15 ptb wake-up from int p p p p p p p p full name general purpose i/o port, port c bit name - - ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 read / write (r/w) - - r/w r/w r/w r/w r/w r/w power-on - - u u u u u u /reset and wdt - - u u u u u u 0x16 ptc wake-up from int - - p p p p p p full name general purpose i/o port, port d bit name ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on u u u u u u u u /reset and wdt u u u u u u u u 0x17 ptd wake-up from int p p p p p p p p
EM77950 bb controller 16 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) addr name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 full name general purpose i/o port, port e bit name pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on u u u u u u u u /reset and wdt u u u u u u u u 0x18 pte wake-up from int p p p p p p p p full name general purpose i/o port, port f bit name - - - - - - ptf1 ptf0 read / write (r/w) - - - - - - r/w r/w power-on - - - - - - u u /reset and wdt - - - - - - u u 0x19 ptf wake-up from int - - - - - - p p full name least significant byte of 16-bit free run counter bit name frc7 frc6 frc5 frc4 frc3 frc2 frc1 frc0 read / write (r/w) r r r r r r r r power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x1a lfrc wake-up from int 0 0 0 0 0 0 0 0 full name most significant byte of 16-bit free run counter bit name frcf frce frcd frcc frcb frca frc9 frc8 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x1b hfrc wake-up from int 0 0 0 0 0 0 0 0 full name least significant byte buffer of 16-bit free run counter bit name frcb7 frcb6 frcb5 frcb4 frcb3 frcb2 frcb1 frcb0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x1c lfrcb wake-up from int 0 0 0 0 0 0 0 0 full name serial peripheral interface read register bit name spir7 spir6 spir5 spir4 spir3 spir2 spir1 spir0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x1d spirb wake-up from int p p p p p p p p
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 17 (this specification is subject to change without further notice) addr name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 full name serial peripheral interface write register bit name spiw7 spiw6 spiw5 spiw4 spiw3 spiw2 spiw1 spiw0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x1e spiwb wake-up from int p p p p p p p p full name converting value of adc bit name add7 add6 add5 add4 add3 add2 add1 add0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x1f addata wake-up from int p p p p p p p p full name bit name - - - - - - read / write (r/w) - - - - - - - - power-on - - - - - - - - /reset and wdt - - - - - - - - 0x20 nc wake-up from int - - - - - - - - full name duty of pwm0-low byte bit name dt07 dt06 dt05 dt04 dt03 dt02 dt01 dt00 read / write (r/w) r r r r r r r r power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x21 dt0l wake-up from int p p p p p p p p full name duty of pwm0-high byte bit name dt0f dt0e dt0d dt0c dt0b dt0a dt09 dt08 read / write (r/w) r r r r r r r r power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x22 dt0h wake-up from int p p p p p p p p full name period of pwm0- low byte bit name prd07 prd06 prd05 prd04 prd03 prd02 prd01 prd00 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x23 prd0l wake-up from int p p p p p p p p
EM77950 bb controller 18 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) addr name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 full name period of pwm0- high byte bit name prd0f prd0e prd0d prd0c prd0b prd0a prd09 prd08 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x24 prd0h wake-up from int p p p p p p p p full name duty latch of pwm0-low byte bit name dl07 dl06 dl05 dl04 dl03 dl02 dl01 dl00 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x25 dl0l wake-up from int p p p p p p p p full name duty latch of pwm0-high byte bit name dl0f dl0e dl0d dl0c dl0b dl0a dl019 dl08 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x26 dl0h wake-up from int p p p p p p p p full name duty of pwm1-low byte bit name dt17 dt16 dt15 dt14 dt13 dt12 dt11 dt10 read / write (r/w) r r r r r r r r power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x27 dt1l wake-up from int p p p p p p p p full name duty of pwm1-high byte bit name dt1f dt1e dt1d dt1c dt1b dt1a dt19 dt18 read / write (r/w) r r/ r r r r r r power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x28 dt1h wake-up from int p p p p p p p p full name period of pwm1- low byte bit name prd17 prd16 prd15 prd14 prd13 prd12 prd1 prd10 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x29 prd1l wake-up from int p p p p p p p p
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 19 (this specification is subject to change without further notice) addr name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 full name period of pwm1- high byte bit name prd1f prd1e prd1d prd1c prd1b prd1a prd19 prd18 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x2a prd1h wake-up from int p p p p p p p p full name duty latch of pwm1-low byte bit name dl17 dl16 dl15 dl14 dl13 dl12 dl11 dl10 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x2b dl1l wake-up from int p p p p p p p p full name duty latch of pwm1-high byte bit name dl1f dl1e dl1d dl1c dl1b dl1a dl19 dl18 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x2c dl1h wake-up from int p p p p p p p p full name bb address register bit name - - - aar4 aar3 aaar2 aar1 aar0 read / write (r/w) - - - r/w r/w r/w r/w r/w power-on - - - 0 0 0 0 0 /reset and wdt - - - 0 0 0 0 0 0x2d rfaar wake-up from int - - - p p p p p full name bb data buffer bit name rfdb7 rfdb6 rfdb5 rfdb4 rfdb3 rfdb2 rfdb1 rfdb0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x2e rfdb wake-up from int p p p p p p p p full name bb data read/write control register bit name - - - - - rrst rfrd rfwr read / write (r/w) - - - - - r/w r/w r/w power-on - - - - - 0 1 1 /reset and wdt - - - - - 0 1 1 0x2f rfacr wake-up from int - - - - - p p p
EM77950 bb controller 20 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) addr name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 full name bb interrupt flag register bit name csdf tx_aef rx_aff tx_ emptyf rx_off link_ disf lock_outf lock_ inf read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x30 rfintf wake-up from int p p p p p p p p full name dual port registers (64 in total) bit name dpr7 dpr6 dpr5 dpr4 dpr3 dpr2 dpr1 dpr0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on /reset and wdt 0x40 ~ 0x7f dpr wake-up from int p p p p p p p p full name peripheral function enable bit name spie - bbe ade pwm1e pwm0e tcce frce read / write (r/w) r/w - r/w r/w r/w r/w r/w r/w power-on 0 - 0 0 0 0 0 0 /reset and wdt 0 - 0 0 0 0 0 0 0x80 prie wake-up from int p - p p p p p p full name interrupt enable control register bit name gie rbfie pwm1ie pwm0ie eint1e eint0e tccoe frcoe read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x81 inte wake-up from int p p p p p p p p full name port a key wake up interrupt enable control register bit name - - - - kwube kwuae kwu9e kwu8e read / write (r/w) - - - - r/w r/w r/w r/w power-on - - - - 0 0 0 0 /reset and wdt - - - - 0 0 0 0 0x82 kwuaie wake-up from int - - - - p p p p full name port b key wake up interrupt enable control register bit name kwu7e kwu6e kwu5e kwu4e kwu3e kwu2e kwu1e kwu0e read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x83 kwubie wake-up from int p p p p p p p p
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 21 (this specification is subject to change without further notice) addr name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 full name external interrupt edge control bit name - - - - - eint1ed eint0ed read / write (r/w) - - - - - r/w r/w power-on - - - - - 0 0 /reset and wdt - - - - - 0 0 0x84 einted wake-up from int - - - - - p p full name serial peripheral serial (spi) enable control register bit name spi_rbf ces sbr2 sbr1 sbr0 sdid sdod spis read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x85 spic wake-up from int p p p 0 0 0 0 0 full name i/o control of port a bit name ioca7 ioca6 ioca5 ioca4 ioca3 ioca2 ioca1 ioca0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 0x86 ioca wake-up from int p p p p p p p p full name i/o control of port b bit name iocb7 iocb5 iocb5 iocb4 iocb3 iocb2 iocb1 iocb0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 0x87 iocb wake-up from int p p p p p p p p full name i/o control of port c bit name - - iocc5 iocc4 iocc3 iocc2 iocc1 iocc0 read / write (r/w) - - r/w r/w r/w r/w r/w r/w power-on - - 1 1 1 1 1 1 /reset and wdt - - 1 1 1 1 1 1 0x88 iocc wake-up from int - - p p p p p p full name i/o control of port d bit name iocd7 iocd6 iocd5 iocd4 iocd3 iocd2 iocd1 iocd0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 0x89 iocd wake-up from int p p p p p p p p
EM77950 bb controller 22 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) addr name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 full name i/o control of port e bit name ioce7 ioce6 ioce5 ioce4 ioce3 ioce2 ioce1 ioce0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 0x8a ioce wake-up from int p p p p p p p p full name i/o control of port f bit name - - - - - - iocf1 iocf0 read / write (r/w) - - - - - - r/w r/w power-on - - - - - - 1 1 /reset and wdt - - - - - - 1 1 0x8b iocf wake-up from int - - - - - - p p full name pull-up control of port a bit name puca7 puca6 puca5 puca4 puca3 puca2 puca1 puca0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x8c puca wake-up from int p p p p p p p p full name pull-up control of port b bit name pucb7 pucb6 pucb5 pucb4 pucb3 pucb2 pucb1 pucb0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x8d pucb wake-up from int p p p p p p p p full name pull-up control of port c bit name - - pucc5 pucc4 pucc3 pucc2 pucc1 pucc0 read / write (r/w) - - r/w r/w r/w r/w r/w r/w power-on - - 0 0 0 0 0 0 /reset and wdt - - 0 0 0 0 0 0 0x8e pucc wake-up from int - - p p p p p p full name pull-up control of port d bit name pucd7 pucd6 pucd5 pucd4 pucd3 pucd2 pucd1 pucd0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x8f pucd wake-up from int p p p p p p p p
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 23 (this specification is subject to change without further notice) addr name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 full name pull-up control of port e bit name puce7 puce6 puce5 puce2 puce3 puce2 puce1 puce0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x90 puce wake-up from int p p p p p p p p full name pull-up control of port f bit name - - - - - - pucf1 pucf0 read / write (r/w) - - - - - - r/w r/w power-on - - - - - - 0 0 /reset and wdt - - - - - - 0 0 0x91 pucf wake-up from int - - - - - - p p full name open drain control of port b bit name opcb7 opcb6 opcb5 opcb4 opcb3 opcb2 opcb1 opcb0 read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x92 odcb wake-up from int p p p p p 0 0 0 full name time clock/counter control bit name - - - - tccs0 ps2 ps1 ps0 read / write (r/w) - - - - r/w r/w r/w r/w power-on - - - - 0 0 0 0 /reset and wdt - - - - 0 0 0 0 0x93 tccc wake-up from int - - - - p p p p full name free run counter control bit name - osco2e osco2sl1 osco2sl0 ppscl2 ppscl1 ppscl0 frccs read / write (r/w) - r/w r/w r/w r/w r/w r/w r/w power-on - 0 0 0 0 0 0 0 /reset and wdt - 0 0 0 0 0 0 0 0x94 frcc wake-up from int - p p p p p p p full name watchdog timer control bit name green - - wdtce - rat2 rat1 rat0 read / write (r/w) r/w - - r/w - r/w r/w r/w power-on 0 - - 0 - 0 0 0 /reset and wdt 0 - - 0 - 0 0 0 0x95 wdtc wake-up from int 0 - - p - p p p
EM77950 bb controller 24 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) addr name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 full name adc analog input pin select bit name - - ims2 ims1 ims0 ckr2 ckr1 ckr0 read / write (r/w) - - r/w r/w r/w r/w r/w r/w power-on - - 0 0 0 0 0 0 /reset and wdt - - 0 0 0 0 0 0 0x96 adcais wake-up from int - - p p p p p p full name adc configuration register bit name adrun adie - - aips3 aips2 aips1 aips0 read / write (r/w) r/w r/w - - r/w r/w r/w r/w power-on 0 0 - - 0 0 0 0 /reset and wdt 0 0 - - 0 0 0 0 0x97 adccr wake-up from int p p - - p p p p full name pwm control register bit name - - - - s_pwm1 s_pwm0 - - read / write (r/w) - - - - r/w r/w - - power-on - - - - 0 0 - - /reset and wdt - - - - 0 0 - - 0x98 pwmcr wake-up from int - - - - p p - - full name bb interrupt enable control register bit name csde tx_aee rx_afe tx_ emptye rx_ofe link_ dise lock_oute lock_ ine read / write (r/w) r/w r/w r/w r/w r/w r/w r/w r/w power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x99 rfinte wake-up from int p p p p p p p p full name open drain control of port c bit name - - opcc5 opcc4 opcc3 opcc2 opcc1 opcc0 read / write (r/w) - - r/w r/w r/w r/w r/w r/w power-on - - 0 0 0 0 0 0 /reset and wdt - - 0 0 0 0 0 0 0x9a odcc wake-up from int - - p p p p p p
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 25 (this specification is subject to change without further notice) 7 function description 7.1 special purpose registers the special purpose registers are function-oriented registers used by the cpu to access memory, record execution results, and carry out the desired operation. the functions of the registers related to the core are described in the following subsections 7.1.1 accumulator ? acc internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the accumulator, which is not an addressable register. 7.1.2 indirect addressing contents ? iac0 (0x00), and iac1 (0x09) the contents of r0 and r9 are implemented as indirect addressing pointers if any instruction uses r6 and r8 as registers. 7.1.3 high byte program counter hpc (0x01) and low byte program counter lpc (0x02) ? program counter (pc) is composed of registers hpc and lpc. ? pc and the hardware stacks are 14 bits wide. ? the structure is depicted in fig. 6-1. ? generates 12k 16 on-chip rom addresses to the corresponding program memory (rom).
EM77950 bb controller 26 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) ? all the bits of pc are set "0"s as a reset condition occurs. ? "ret" ("retl k", "reti") instruction loads the program counter with the contents at the top of stack. ? "mov r2, a" allows the loading of an address from the "a" register to the lower 8 bits of the pc, and the high byte (a8~a14) of the pc remain unchanged. ? "add r2, a" & "tbl" allows a corresponding address / offset be added to the current pc. 7.1.4 status register ? sr (0x03) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - rst t p z dc c bit 0 (c): carry flag. this bit indicates that a carry out of alu occurred during the last arithmetic operation. this bit is also affected during bit test, branch instruction and bit shifts. bit 1 (dc): auxiliary carry flag. this bit is set during add and adc operations to indicate that a carry occurred between bit 3 and bit 4. bit 2 (z): zero flag. set to "1" if the result of the last arithmetic, data or logic operation is zero. bit 3 (p): power down bit. set to 1 during power on or by a "wdtc" command and reset to 0 by a "slep" command. bit 4 (t): time-out bit. set to 1 by the "slep" command and the "wdtc" command, or during power up and reset to 0 by wdt timeout. bit 5 (rst): set if the cpu wakes up by keying wake-up pins. reset if the chip wakes up from other ways. bits 6 and 7 are reserved. 7.1.5 ram bank selector ? rambs0 (0x04), and rambs1 (0x07) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - - rambsx2 rambsx1 rambsx0 as depicted in fig. 6-2, there are seven available banks in the mcu. each of them have 128 registers and can be accessed by defining the bits, rambsx0 ~ rambsx2, as shown below.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 27 (this specification is subject to change without further notice) rambsx (0x04/0x07) bank 000 0 010 2 011 3 100 4 101 5 110 6 7.1.6 rom page selector ? romps (0x05) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - - - - rps0 as depicted in fig. 6-1, there are two available pages in mcu. the first page has 8k 16 rom size and the second page has 4k 16 rom size. both of them can be accessed by defining the bits, rps0, as shown below. as depicted in fig. 6-1, there are two available pages in the mcu. each page has 12k 16 rom size and can be accessed by defining the bits, rps0, as shown below. rps0 page (address) 0 0 (0x0000~0 1fff) 1 1 (0x2000~0 2fff) 7.1.7 indirect addressing pointers ? iap0 (0 06), and iap1 (0 08) both r6 and r8 are not physically implemented registers. they are useful as indirect addressing pointers. any instruction using r6/r4 and r8/r7 as registers actually access data pointed by r0 and r9 individually. 7.1.8 indirect address pointer direction control register ? iapdr (0x0a) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - iap1_d iap0_d iap1_d_e iap0_d_e bit 0/1 (iap0_d_e/iap1_d_e) indirect addressing pointer0/1 direction function enable bit. 0 : disable 1 : enable bit 2/3 (iap0_d/iap1_d) indirect addressing pointer0/1 direction control bit. 0 : minus direction 1 : plus direction
EM77950 bb controller 28 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 7.1.9 table look-up pointer ? ltbl (0x0b), and htbl (0x0c) the maximum length of a table is 64k, and can be accessed through registers ltbl and htbl. htbl is the high byte of the pointer, whereas ltbl is the low byte. 7.1.10 stack pointer ? stkptr (0x0d) register rd indicates how many stacks the current free run program uses. it is a read only register. 7.1.11 repeat counter ? rptc (0x0e) the re register is used to set how many times the ?rpt? instruction is going to read the table. 7.1.12 prescaler counter ? prc (0x0f) prescaler counter for tcc. 7.1.13 real time clock counter ? rtcc (0x10) tcc counter. 7.1.14 interrupt flag register ? intf (0x11) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adif rbfif pwm1if pwm0if eint1f eint0f tccof frcof bit 0 (frcof): frc overflow interrupt. set as the contents of the frc counter change from 0xffff to 0x0000, reset by software. bit 1 (tccof): tcc overflow interrupt. set as the contents of the tcc counter change from 0xff to 0x00, reset by software. bits 2 ~ 3 (eint0f & eintif): external input pin interrupt flag. interrupt occurs at a defined edge of the external input pin, reset by software. bits 4 ~ 5 (pwm0if & pwm1if) : pwm interrupt flag. interrupt occurs when tmrx is equal to prdx, reset by software. bit 6 (rbfif): spi receiving buffer full interrupt flag. interrupt occurs when an 8-bit data is received, reset by software. bit 7 (adif): adc conversion complete interrupt flag. each bit can function independently regardless whether its related interrupt mask bit is enabled or not.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 29 (this specification is subject to change without further notice) 7.1.15 key wake-up flag register ? kwuaif (0x12) & kwubif (0x13) kwuaif: port a key wake-up interrupt flag bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - kwubif kwuaif kwu9if kwu8if kwubif: port b key wake-up interrupt flag bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 kwu7if kwu6if kwu5if kwu4if kwu3if kwu2if kwu1if kwu0if 7.1.16 i/o port registers ? pta ~ ptf (0x14 ~ 0x19) ptx can be operated by related instructions, as any other general purpose registers. that is, ptx is an 8-bit, bidirectional, general purpose port. its corresponding i/o control bit determines the data direction of a ptx pin. 7.1.17 16-bit free run counter (f rc) ? lfrc (0x1a), hfrc (0x1b) & lfrcb (0x1c) r1a is 16-bit frc low byte; r1b is high byte; r1c is low byte buffer. 7.1.18 serial peripheral interfac e read register ? spirb (0x1d) register r1d indicates spi received data. 7.1.19 serial peripheral interf ace write register ? spiwb (0x1e) register r1e indicates spi transmitted data. 7.1.20 adc converting value ? addata (0x1f) addata: converting value of adc. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 add7 add6 add5 add4 add3 add2 add1 add0 7.1.21 pwm duty ? dt0l (0x21)/dt0h (0x22) & dt1l (0x27) / dt1h (0x28) r22 : r21 16-bit pwm0 output duty cycle. r28 : r27 16-bit pwm1 output duty cycle. 7.1.22 pwm period ? prd0l (0x23)/prd0h (0x24) & prd1l (0x29)/prd1h (0x2a) r24 : r23 16-bit pwm0 output period cycle. r2a : r29 16-bit pwm1 output period cycle.
EM77950 bb controller 30 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 7.1.23 pwm duty latch ? dl0l (0x25)/dl0h (0x26) & dl1l (0x2b)/dl1h (0x2c) r26 : r25 16-bit pwm0 output duty cycle buffer. r2c : r2b 16-bit pwm1 output duty cycle buffer. 7.1.24 bb address register ? rfaar (0x2d) register r2d indicates bb indirect ram address. 7.1.25 bb data buffer register ? rfdb (0x2e) register r2e indicates bb indirect ram data. 7.1.26 bb data read/write control register ? rfacr (0x2f) register r2f indicates bb ram access control. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - - rrst rfrd rfwr bit 0 (rfwr): write bb register. bit 1 (rfrd): read bb register bit 2 (rrst): bb s/w reset. bit 3 ~ bit 7: reserved 7.1.27 bb interrupt flag register ? rfintf (0x30) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 csdf tx_aef rx_aff tx_ emptyf rx_off link_ disf lock_outf lock_ inf bit 0 (lock_inf): this bit reflects the lock in flag interrupt. bit 1 (lock_outf): this bit reflects the lock out flag interrupt. bit 2 (link_disf): this interrupt is invoked by the zero counter capacitor discharge mechanism. bit 3 (rx_off): this bit reflects the rx fifo full flag interrupt. bit 4 (tx_emptyf): this bit reflects the tx empty flag interrupt. bit 5 (rx_aff) : this bit reflects the rx fifo almost full flag interrupt. bit 6 (tx_aef) : this bit reflects the tx fifo almost empty flag interrupt. bit 7 (csdf): this flag indicates that a carrier-sense interrupt has occurred.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 31 (this specification is subject to change without further notice) 7.2 dual port register (0x40 ~ 0x7f) r 40 ~ r7f are dual port registers. 7.3 system status, control and configuration registers these registers are function-oriented registers used by the cpu to record, enable or disable the peripheral modules, interrupts, and the operation clock modes. 7.3.1 peripherals enable control ? prie (0x80) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spie - bbe ade pwm1e pwm0e tcce frce bit 0 (frce): free run counter 0 (frc0) enable bit. bit 1 (tcce): timer clock/counter (tcc) enable bit. bit 2 (pwm0e): pwm0 function enable bit. bit 3 (pwm1e): pwm1 function enable bit. bit 4 (ade): adc enable bit. bit 5 (bbe): base band (bb) enable bit. bit 7 (spie): serial peripheral interface enable bit. 0 : disable function 1 : enable function 7.3.2 interrupts enable control ? inte (0x81) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gie rbfie pwm1ie pwm0ie eint1e eint0e tccoe frcoe bit 0 (frc0oe): free run counter (frc) overflow interrupt enable bit. bit 1 (tccoe): tcc (tcc) overflow interrupt enable bit. bit 2 (eint0e): external pin (eint0) interrupt enable bit. bit 3 (eint1e): external pin (eint1) interrupt enable bit. bits 4 (pwm0ie): pwm0 period complete enable bit. bits 5 (pwm1ie): pwm1 period complete enable bit. bit 6 (rbfie): spi read buffer full (eint) interrupt enable bit. 0 : disable function interrupt 1 : enable function interrupt
EM77950 bb controller 32 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) bit 7 (gie): global interrupt control bit. global interrupt is enabled by the eni and reti instructions and is disabled by the disi instruction. 0 : disable global interrupt function 1 : enable global interrupt function 7.3.3 key wake-up enable control ? kwuaie (0x82) & kwubie (0x83) kwuaie: port a key wake-up interrupt enable control register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - kwube kwuae kwu9e kwu8e bit 0 ~bit 3 (kwu8e ~ kwube): enable or disable the pta0 ~ pta3 key wake-up function. 0 : disable key wake-up function 1 : enable key wake-up function kwubie: port b key wake-up interrupt enable control register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 kwu7e kwu6e kwu5e kwu4e kwu3e kwu2e kwu1e kwu0e bit 0 ~bit 7 (kwu0 ~ kwu7): enable or disable the ptb0 ~ ptb7 key wake up function. 0 : disable key wake-up function 1 : enable key wake-up function 7.3.4 external interrupts edge control ? einted (0x84) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - - - eint1ed eint0ed bit 0 (eint0ed): define which edge as an interrupt source for eint0. bit 1 (eint1ed): define which edge as an interrupt source for eint1. 0 : falling edge 1 : rising edge bit 2 ~ bit 7 reserved
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 33 (this specification is subject to change without further notice) 7.3.5 serial peripheral serial (spi) enable control register ? spic (0x85) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spi_rbf ces sbr2 sbr1 sbr0 sdid sdod spis bit 0 (spis): spi start. bit 1 (sdod): spi data shift out direction. 0 : most significant bit (msb) transmitted first 1 : least significant bit (lsb) transmitted first bit 2 (sdid): spi data shift in direction. 0 : most significant bit (msb) received first 1 : least significant bit (lsb) received first bit 3 ~ 5 (sbr0 ~ sbr2): configure the transmission mode and the clock rate. sbr2 (bit5) sbr1 (bit4) sbr0 (bit3) mode baud rate 0 0 0 master fosc/2 0 0 1 master fosc/4 0 1 0 master fosc/8 0 1 1 master fosc/16 1 0 0 master fosc/32 1 0 1 slave n/a 1 1 0 n/a n/a 1 1 1 n/a n/a bit 6 (ces): clock edge select bit. 0 : data shifts out on a rising edge, and shifts in on a falling edge. data is held during a low level 1 : data shifts out on falling edge, and shifts in on rising edge. data is hold during the high level bit 7 (spi_rbf): spi read buffer full flag. 7.3.6 i/o control registers ? ioca~iocf (0x86~0x8b) iocx is used to determine the data direction of its corresponding i/o port bit. 0 : configure a selected i/o pin as output 1 : configure a selected i/o pin as input the only four least significant bits of port f, and the only five least significant bits of port c are available.
EM77950 bb controller 34 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 7.3.7 pull-up resistance control registers for ports a~f ? puca~pucf (0x8c ~ 0x91) each bit of pucx is used to control the pull-up resistors attached to its corresponding pin respectively. the theoretical value of the resistor is 64 k . however, due to process variation, 35% variation in resistance must be taken into consideration. pucx: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pucx7 pucx6 pucx5 pucx4 pucx3 pucx2 pucx1 pucx0 0 : pull-up resistors disconnected 1 : pull-up resistors attached 7.3.8 open drain control registers of port b/port c ? odcb/odcc (0x92/0x9a) odcb/odcc: open drain control of port b/port c. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 opcx7 opcx6 opcx5 opcx4 opcx3 opcx2 opcx1 opcx0 0 : open drain disable 1 : open drain enable 7.3.9 timer clock counter controller ? tccc (0x93) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - tccs0 psr2 psr1 psr0 bit 0 ~ 2 (psr0 ~ psr2): prescaler for tcc. psr2 psr1 psr0 clock rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 bit 3 (tccs0): clock source select. tccs0 clock source 0 selected pll clock source 1 selected irc clock source bits 4 ~ 7 are reserved.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 35 (this specification is subject to change without further notice) 7.3.10 free run counter controller ? frcc (0x94) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - osco2e osco2sl1 osco2sl0 ppscl2 ppscl1 ppscl0 frccs bit 0 (frccs): clock source select. frccs clock source 0 selected pll clock source 1 selected irc clock source bits 1 ~ 3 (psr0 ~ psr2): prescaler for the osco2 clock output. ppscl2 ppscl1 ppscl0 clock rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 bit 4 and bit 5 (osco2sl0 and osco1sl1): system clock frequency select control bits osco2sl0 osco2sl1 output frequency (mhz) 0 0 6 0 1 12 1 0 24 1 1 48 bit 6 (osco2e): osco2 output function mask. . 0 : osco2 disabled, function as pin pf0; 1 : osco2 enabled. bit 7 reserved. 7.3.11 watchdog timer controller ? wdtc (0x95) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 green - - wdtce - rat2 rat1 rat0
EM77950 bb controller 36 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) bit 0 ~ 2 (rat0 ~ rat2): prescaler of wdt. rat2 rat1 rat0 clock rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 bit 4 (wdtce): enable the wdt counter 0 : wdt disabled; 1 : wdt enabled. bits 7 (green): for the reason of power saving, the system clock can be changed to internal rc mode. 1 : green mode 0 : normal mode bits 3, 5 and 6 are reserved. 7.3.12 adc analog input pi n select ? adcais (0x96) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - ims2 ims1 ims0 ckr1 ckr0 ckr0 ~ ckr2 (bit 0 ~ bit 2) : ad conversion rate control bits. ims2~ims0 (bit 2 ~ bit 4): adc configuration definition bit. bits 5 ~ 7 are reserved. 7.3.13 adc configuration register ? adccr (0x97) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adrun adie - - aips3 aips2 aips1 aips0 bit 0 ~ bit3 (aips0~aips3): analog input select. bit 6 ~ bit 7 (adie): adc interrupt enable. 0 : adc interrupt disable 1 : adc interrupt enable
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 37 (this specification is subject to change without further notice) bit 7 (adrun): adc starts to run 0 : reset on completion of the conversion; this bit cannot be reset by software. 1 : a/d conversion is started; this bit can be set by software. bits 4 and 5 are reserved. 7.3.14 pwm control register ? pwmcr (0x98) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - s_pwm1 s_pwm0 - - bit 2 (s_pwm0): selected pwm0 output enable. bit 3 (s_pwm1): selected pwm1 output enable. 0 : disable pwm output 1 : enable enable pwm output bits 0, 1 and 4 ~ 7 are reserved. 7.3.15 bb interrupt control register ? rfinte (0x99) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 csde tx_aee rx_afe tx_ emptye rx_ofe link_ dise lock_ou te lock_ ine bit 0 (lock_ine): lock in interrupt enable bit. bit 1 (lock_oute): lock out interrupt enable bit. bit 2 (link_dise): link_dis interrupt enable bit. bit 3 (rx_ofe): rx fifo full interrupt enable bit. bit 4 (tx_emptye): tx empty interrupt enable bit. bit 5 (rx_afe): rx fifo almost full interrupt enable bit. bit 6 (tx_aee): tx fifo almost empty interrupt enable bit. bit 7 (csde): carrier-sense interrupt enable bit. 0 : disable interrupt function 1 : enable interrupt function
EM77950 bb controller 38 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 7.4 code option (rom-0x2fff) register sclk is located on the very last bit of EM77950?s 12k program rom. these values will be fetched first to be the system initial values as power-on. sclkc: system clock control register sclkc bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x2fff - - - rfclk1 rfclk0 sclk1 sclk0 sclkc bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0x2fff - - - - - - - - bit 1 ~ bit 2 (sclks1 ~ sclks0): system clock frequency select control bits sclk1 sclk0 system clock (mhz) 0 0 6 0 1 12 1 0 24 1 1 48 bit 3 ~ bit 4 (rfck1 ~ rfck0): wireless modem clock frequency select control bits rfclk1 rfclk0 system clock (mhz) 0 0 6 0 1 12 1 0 24 1 1 48 bit5 ~ 15: reserved sclk [1:0] rfclk [1:0] wdt_con.green sys clk rf clk note 00 00 0 bypass bypass 1~20mhz (6mhz) 00/01/10/11 01/10/11 0 6/12/24/48 12/24/48 01/10/11 00/01/10/11 0 12/24/48 6/12/24/48 00/01/10/11 00/01/10/11 1 irc 6/12/24/48 bb enable
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 39 (this specification is subject to change without further notice) 8 baseband (bb) 8.1 bb: standard interface for the rfw102 series 8.1.1 features ? parallel interface to rfw102 modem ? serial to parallel conversion of rfw102 interface ? input fifo (rx_fifo) ? output fifo (tx_fifo) ? preamble correlation ? packet address filter (network and unique) ? crc calculation ? working frequencies: 6-24mhz ? power save modes: idle, power-down ? inter-rfwaves networks carrier-sense ? discharge of the rfw-102 reference capacitor ? compensate for clock drifts between transmitting and the receiving the EM77950 up to 1000ppm. hence, the EM77950 requires low performance crystal. ? interrupt driver ? connected to the EM77950?s internal interrupt and informs the EM77950 about bb events. 8.1.2 description rfwaves has developed a very low cost wireless modem (rfw102) for short range, cost-sensitive applications. the modem is a physical layer element (phy) ? allowing the transmission and reception of bits from one end to the other. in an rfwaves application, the mcu is in charge of the mac layer protocol. in order to reduce the real-time demands of the mcu handling the mac protocol, the bb was developed. the bb enables the mcu an easy interface to rfw102 through a parallel interface, similar to memory access. it converts the fast serial input to 8-bit words, which are much easier for an 8-bit mcu to work with, and requires a lower rate oscillator. it buffers the input through a tbd bytes fifo, enabling the mcu to access the bb more efficiently. instead of reading one byte per interrupt, the mcu can read up to 16 bytes in each interrupt. this reduces the mcu overhead in reading incoming words, insofar as stack stuffing and pipeline emptying are concerned, in cases where each incoming byte causes an interrupt. when using the fifo, the mcu pays the same overhead for all the fifo bytes as it paid for only one byte without a fifo.
EM77950 bb controller 40 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) having a low-cost bb with a built-in state machine that can support basic wireless communication elements presents the following advantages: ? shorter development time, hence shorter time to market. ? conserve cpu power and other resources for other applications. ? offer an easy, standard integrated solution. 8.1.3 i/o and package description mcu bb rfw-102 serial io tx_rx data io tx_rx rf_active shdwn tx_ae tx_ae rx_af tx_empty cs lock_in lock_out rx_af tx_empty cs lock_in lock_out rst cs_n wr_n rd_n rf_active ram_addr [0~6] data [0~7] rd_n wr_n cs_n rst shdwn 7 8 rf clk rf clk ram_addr [0~6] data [0~7] fig. 8-1 parallel interface between the mcu and rfw-102 through bb
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 41 (this specification is subject to change without further notice) name type description data [0-7] i/o this bus comprises of eight tri-state input/output lines. the bus provides bidirectional communication between the system and the mcu. data, control words, and status information are transferred via the data [0-7] data bus. rd_n i when rd_n is low while the system is enabled, bb outputs one of its internal register values to data[0-7] according to ram_addr[0-6]. wr_n i when wr_n is low while the system is enabled, bb enables writing to its internal registers. the register is determined by ram_addr [0-6] and the value data[0-7]. ram_addr[0-6] i these four input signals determine the register to which the mcu writes to or reads from. cs_n i chip select input pin. when cs_n is low, the chip is selected; when high, the chip is disabled. this pin overrides all pins excluding rst. this enables communication between bb and the mcu. this pin functions as wakeup pin for power-down and idle modes. tx_ae; tx_empty; rx_af; cs; lock_in; lock_out o interrupt driver pins. this pin goes high whenever any of the interrupt sources has an active high condition and is enabled via the ier. the purpose of this pin is to notify the mcu through its external interrupt pin that an event (such as empty tx_fifo) has occurred. goes low when ier register is read. rst i chip?s reset pin. when this pin is set high, all registers and fifos are cleared to their initial values. all transceiver traffic is disabled and aborted. reset is asynchronous to system clock. after power-up, a pulse in rst input should be applied (by por). shdwn i shut down bb rf_active o this output pin controls the rfw102 working/shutdown mode. its values are determined by scr4(1). serial_io i/o serial input or output according to tx_rx mode. it functions as serial interface for the rfw-102 (rfwaves modem). when serial_io is input, it is a schmitt-trigger input. rx_tx o this pin controls rfw-102 operation mode. it should be connected to rfw-102 rx_tx input pin. when rx_tx is low, rfw-102 is in receiving mode. when rx_tx is high, rfw-102 is in transmitting mode. in most cases rx_tx output pin is determined by scr2(0) register. scr3(7) and the capacitor discharge mechanism affects this pin. rf_clk i clock for rf operation
EM77950 bb controller 42 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 8.1.4 bb architecture address bus data bus int rx fifo tx fifo control and status registers receiver preamble correlation address filter crc transmitter interrupt handler parallel interface serial input / output fig. 8-2 bb block diagram 8.2 bb description 8.2.1 reset a reset is achieved by holding the rst pin high for at least tbd oscillator cycles. to ensure good power-up, a reset should be given to bb after power-up. 8.2.2 power saving modes the bb was designed to work in similar working modes as a typical mcu. these modes enable the system to conserve power when the bb is not in use. 8.2.2.1 power-down mode the mcu is able to halt all activity in bb by stopping its clock. this enables the mcu to reduce the power consumption of the bb to a minimum. all registers and fifos retain their values when bb is in power-down mode. bb enters power-down mode by setting bit tbd in register tbd to ?1?. this bit is set by the mcu and cleared by bb. bb goes back to working mode by setting cs_n input pin to ?0? for tbd msec. the wake-up time of bb from power-down mode to fully operating mode is tbd msec.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 43 (this specification is subject to change without further notice) since bb retains all the register values in power-down mode, special care should be paid to the register values before it enters power-down. for example, the mcu should check that the bb is not in the middle of transmitting or receiving a packet. the rfactive should be set low to shutdown the rfw-102, before entering power-down mode. 8.2.2.2 idle mode in idle mode, the bb internally blocks the clock input. the external clock is not stopped, but it is not routed to the internal logic. by doing this, the mcu achieves substantial power savings and yet the wake-up time is still relatively short. the power consumption is not minimal since the external clock is still active. all registers and fifos retain their values when bb is in idle mode. bb enters idle mode by setting bit tbd in regist er tbd to ?1?. this bit is set by the mcu and cleared by bb. bb goes back to working mode by setting cs_n input pin to ?0? for tbd sec. since bb retains all the register values in idle mode, special care should be given to the register values before bb enters idle mode. for example, the mcu should check that the bb is not in the middle of transmission or receiving a packet. in addition, the rfactive should be set low to shutdown the rfw-102. 8.2.3 preamble correlation the transmitting bb sends the preamble in order to synchronize the receiver to its transmission. bb transmits a fixed size preamble of 16 bits. the received preamble has a variable length of 16 9 bits, determined by scr2 [5:7]. the receiver correlates the 16 9 bits from its pre-l and pre-h registers to the 16 9 bits in its input shift-register. if a correlation was found, then bb receiver state machine is enabled. the purpose of the preamble is to filter the module packets from white noise or other transmissions on the channel. node_id and net_id filter are used to filter packets from other module networks. the preamble is transmitted msb to lsb (pre-h first and then pre-l). the value of the preamble is determined according to pre-l and pre-h registers. the bb has the same preamble when it is in transmitting mode (tx_rx=1) as when it is in receiving mode (tx_rx=0). the value of the pre-l and pre-h registers should be identical in the bb in all nodes in the network.
EM77950 bb controller 44 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 8.2.4 refresh bit when receiving a valid packet, the rfwaves modem (phy layer) has to receive a ?1? symbol each time a certain period has elapsed in order to maintain its sensitivity. the time between adjacent ?1? symbols is determined by the value of the reference capacitor. this constraint is transparent to the application layer since the bb adds a ?1? symbol (refresh bit) if too many ?0? symbols are transmitted consecutively. on the receiver side, these additional ?1? symbols (refresh bits) are removed by the bb. this feature is transparent to the application layer. the application layer has only to initialize the maximum allowed number of consecutive x?00? bytes. the bb has the flexibility to add a refresh bit every 1 to 7 bytes. this is configured by rb (0:2) bits in ppr register. the value of rb (0:2) bits in ppr register determines the overhead the refresh bit has on the throughput of the link. the refresh bit does not add substantial overhead on the bit stream, since it is only added when the number of consecutive x?00? bytes exceeds a certain value. the data that is sent is application dependent, so the application can be adjusted in order that there will be a negligible probability of this event happening. typical rfwaves capacitor: c=1nf. normal discharge current = 200na. each 10mv on the capacitor represent 1db in receiving power. sec 50 1 10 1 200 db mv nf na v c i = ? = ? the capacitor is charged with each received ?1? symbol. the receiver is allowed to lose 1db before a new ?1? is to be received. thus, after each 50 consecutive ?0? bits in 1mbps (50 sec) a ?1? symbol should be sent. in this case, setting rb [0:2] in ppr register to be 5 (?101?) would be sufficient (5 bytes = 40bits). when rb (0:2) bits are set to ?000? a refresh bit is added to every transmitted byte, regardless of its content. this introduces a constant overhead of 12.5%. 8.2.5 bit structure the bb uses an oscillator ranging from 6~24 mhz. in order to det ermine the output and input bit rate, the bb must be configured to the number of clocks consisting each bit. this gives the applicator the control over the bit rate with certain restrictions. each bit must have at least 6 clock cycles.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 45 (this specification is subject to change without further notice) the maximum bit rate is: 1mbps. the minimum bit rate is: 10kbps (tbd) however it is recommended to work only at 1mbps since reducing the bit rate does not change the energy of a transmitted bit. meaning, reducing the bit-rate does not improve the bit error rate or the range between the transmitter and the receiver. bit length register (blr) determines the number of clock cycles per bit (bit period). blr value is given a fixed offset of 6, since the minimum number of clock cycles in one bit is 6. bit rate = oscillator/(blr+6). the bb outputs (for the rfw-102) the bit structure shown below. bit "1" structure - even clock number clock period bit period bit "1" structure - odd clock number clock period bit period fig. 8-3 bit structure of the bb output to the rfw-102 in the odd number of clocks example blr=1. in the even number of clocks example blr=2. the number of clocks when the line is ?1? is determined as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = 1 2 6 " 1 " blr floor s of number in case of ?0? bit, bb output ?0? value for blr+6 clock pulses. * floor ? rounds towards zero. 8.2.6 crc the bb adds additional crc information to each packet in the transmitter module, in order to enable the protocol to detect errors. the crc is a redundant code, which is calculated and added to each packet on the transmitter side. the crc is also calculated on the receiver side. the crc calculation results of the receiver and the crc field in the received packet are compared in the receiver using the crc module in the chip. if crc results are equal, then the receiver knows with reasonable probability that the packet was received correctly. if the crc results are not equal then the receiver knows with probability 1 that the packet was received incorrectly. the crc mode is configured in the ppr (3:4) register.
EM77950 bb controller 46 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) both the receiving node and the transmitting node in the network have to be in the same crc mode. the bb can apply crc in three different ways: 16-bit crc ? using polynomial 1+x 2 +x 15 +x 16 . 8-bit crc ? using polynomial 1+x+x 2 +x 8 . no crc. this gives each application the flexibility to choose the adequate amount of overhead it adds to each packet and the corresponding level of protection the crc code has. if crc is enabled, then bb calculates the crc of each incoming packet. it does not put the received crc value in the rx_fifo. it just puts the result of its calculation in the rx_fifo as the last byte of the packet: 0x55 ? crc received correctly. 0xaa ? crc was received incorrectly. the status bit ssr (0) stores the result of the last received packet. 8.2.7 rx fifo all received bytes are transferred to the rx_fifo. the rx_fifo stores the input data until the mcu reads the data from it. crc and preamble bytes are not transferred to the rx_fifo. the rx_fifo is accessed just like all the other read-only registers in the bb. the mcu cannot write to rx_fifo - it can only read from it. rx_fifo_size is 16 bytes. the purpose of having an input fifo in bb is to reduce the real-time burden from the mcu. the fifo is used as a buffer, which theoretically enables the mcu to read the incoming data every rx_fifo_size 8 bit/byte 1 sec = 128 sec, and not every 1 sec in the case of serial input, or every 8 sec in the case where there is a serial to parallel converter. the actual buffer size for practical use is a bit smaller, since the mcu response time is taken into account. the mcu has three ways to learn about the rx_fifo status: the rx fifo status register (rfsr) contains the number of bytes in the rx_fifo. bb int pin . i f configured appropriately, the int pin will be ?1? each time rx_fifo is almost full. this invokes an mcu interrupt if the int pin is connected to the mcu external interrupt pin.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 47 (this specification is subject to change without further notice) rx_fifo overflow status bit ? bit rx_of in ssr indicates when an overflow event has occurred. if a received byte is written to a full rx_fifo, the last byte in the rx_fifo is override and the rx_of flag is raised. the rx_af interrupt should invoke the mcu to read from the rx_fifo. using the almost full event gives the mcu 32 sec (4 bytes 8 sec) to respond before it loses data, assuming a bit rate of 1mbps. it uses most of the rx_fifo size even if the response latency of the mcu is very short. should the mcu not respond properly to the almost full event, and an input byte is written to the rx_fifo when it was full, then this byte would overrun the last byte in the rx_fifo, meaning the byte that immediately preceded it. lock_out interrupt should also trigger the mcu to read from the rx_fifo. in case a packet has ended and the rx_af interrupt was not invoked, the mcu should be triggered by the lock_out interrupt. 8.2.8 tx fifo transmitting data is done by writing it to the tx_fifo. the interface to the tx_fifo is similar to all the other write-only registers in bb. the purpose of the tx_fifo is to reduce the real-time from the mcu in a transmitting process. the tx_fifo enables the mcu, t heoretically, to write to the tx_fifo every 128 sec and not every 8 sec, as is the case with a regular 8-bit shift register. the tx_fifo status register (tfsr) indicates the number of bytes in the tx_fifo. the tx_fifo can also invoke an mcu interrupt if tx_fifo almost empty event occurs. almost empty flag will rise when there are only 4 empty bytes in the tx_fifo. it gives the mcu 32 sec to respond time to reload the tx_fifo in case the transmitted packet is bigger than the tx_fifo. in case the mcu writes to a full tx_fifo, then this byte overruns the last byte in the tx_fifo, meaning the byte that was written just before it. writing to a full tx_fifo set the tx_of flag in ssr. 8.2.9 interrupt driver the int output pin is the summation of all interrupt sources in the bb. whenever an interrupt event has occurred and this interrupt is enabled (ier), int will go from low to high. int will remain high until iir register is read. the iir register contains all the interrupts event that have occurred since the last read. it shows the event only for enabled interrupts. if an interrupt is disabled, even if the event that invoked this interrupt has occurred, the interrupt flag w ill be low. the ier register is used to enable/disable each of the interrupt. scr4 (0) enables/disables all the interrupts.
EM77950 bb controller 48 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) there are 8 events in the bb that can cause the int pin to go from low to high: 1. lock_in ? this interrupt indicates that the bb has started receiving a new packet. the preamble has been identified. if the net_id or/and the node_id are enabled, then they have been identified correctly. this event signals the beginning of an incoming packet. 2. lock out ? bb has just finished receiving a packet. this means that if the bb is in fixed packet size mode, then it has finished receiving psr bytes not including crc bytes. if bb is not in fixed packet size mode, then it has just finished receiving a packet of size as indicated in the packet header. although rx_stop and setting tx_rx=1 (scr2) terminate the receiving of the packet, they do not cause a lock_out event, since the mcu is already aware of it (the mcu initiated it). the lock_out interrupt tells the mcu when to get data out of the rx_fifo. 3. link_dis ? this interrupt indicates that a ?zero counter? capacitor discharge event has occurred. if a consecutive number of zero bits (according to scr3 (4:6)) have been received, this interrupt is set, even if zero count capacitor discharge is disabled (scr3 (3) ? en_zero_dis = ?0?). the actual capacitor discharge and its interrupt are two separate registers (ier (2) for the interrupt and scr3 (3) for the discharge). 4. rx_of ? this interrupt indicates that a byte from an incoming packet was discarded, since the rx_fifo was already full. the receiver module tried to write a byte to a full rx_fifo. the mcu should know that the corresponding packet is corrupted, since it is lacking at least one byte. 5. tx_empty ? the bb has finished transmitting a packet. meaning, the transmit shift register is empty and bb is now in rx mode (not tx mode). 6. rx_fifo_af ? rx_fifo is almost full. if the mcu does not want the rx_fifo to overflow, then it should empty it. 7. tx_fifo_ae ? tx_fifo is almost empty. if the mcu did not finish putting the transmitted packet in the tx_fifo, then it should continue doing so now. 8. cs ? cs status line has gone from ?1? to ?0? invokes a cs interrupt. this signals the mcu that an unidentified (net_id or node_id or preamble were not identified) packet has ended. if the mcu has a packet to transmit, and cs=?1? than the mcu waits for this event. all these events can be masked. if an event is masked, then even if that event occurs - it does not set the int pin to ?1?. the masking is done by register ier. the reason for masking is that in different applications or in different situation in the same application these events have different priorities. the mcu determines which of these events will invoke an mcu interrupt.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 49 (this specification is subject to change without further notice) moreover all these events can be masked together by ie in ier register. if int pin is set to ?1?, the mcu learns which event has occurred by reading iir register. int goes ?0? when mcu reads from iir register. 8.2.10 packet size there are two types of packet structure determined by ppr [5] (fixed). fixed sized packet ? all packets have the same, fixed size. the packet size is determined in psr register. the packet size can be 2 ~ 255 bytes. variable sized packet - the header of the incoming packet determines the packet size. one of the header bytes contains the packet size. bits size_loc[0:1] in lcr register determines the location (offset) of the packet size inside each incoming packet header. the bb reads the packet size byte in the packet header according to lcr register. in both cases the packet size does not include the crc addition or the preamble. 8.2.11 net_id and node_id filters net_id and node_id are two filters in the receiver. they filter incoming packets according to their network address and node address. the address field in each incoming packet is compared to net_id byte and node_id byte. if one of the above comparisons fails, then the packet is discarded and the mcu will not be aware of it. net_id and node_id are both one byte. their values are stored in nir and bir registers accordingly. the byte to which they are compared is set by the lcr register. each of them can be enabled or disabled independently (ppr register). net_id is targeted to be a filter on the network address. it is supposed to be common for all nodes in the network. node_id is targeted to be a filter on the specific node address. it is supposed to be unique to each node in the network. the purpose of these filters is to conserve mcu power and to reduce its load. in a multi-node network, a node can filter all packets that are not sent to it, while in multi-network environment, a node can filter packets from other rfwaves networks. in certain network, a multicast ability inside the network is required. even if node_id filter is applied, addresses ?111111xx? in node_id filter are preserved for multicast transmissions. node_id filter will not discard those 4 addresses in any case.
EM77950 bb controller 50 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 8.2.12 carrier-sense carrier-sense protocols are protocols in which a node (station) listens to the common channel before it starts transmitting. the node tries to identify other transmissions in order to avoid collision that might block its own transmission. in a wider perspective, a network that applies carrier-sense protocol utilizes the channel bandwidth more efficiently. a more efficient network enables lower power consumption to each node, shorter delay and higher probability of re aching destination to each packet. the bb uses one complimentary technique in order to achieve very wide-ranging carrier-sense abilities. it has an internal implementation of rfwaves network carrier-sense algorithm. this enables it to avoid collision with other rfwaves stations on its network or from other networks in the area. while the carrier-sense status bit in ssr (cs) tells the mcu when not to transmit, the two interrupt cs and link_dis gives the mcu a flag when to transmit. link_dis will be invoked whenever any transmission has ended, while cs interrupt will be invoked only when an rfwaves transmission has ended. an application can use some of the above mechanisms though not all of them ? according to its needs. 8.2.12.1 rfwaves carrier-sense algorithm assuming our bit rate is 1mbps. according to the described bit structure (section 8.2.5 bit structure), the time difference between two rising on data_io must be an integer number of 1 sec. if we take into account the frequency deviation between the two bb oscillators, the time difference between two rising edges is 1 sec. the depends on the frequency deviation between the two bb oscillators. the bb uses this quality in its carrier-sense algorithm. if an n (n = (csr (0:3) * 2) + 2) number of ?1? bit, where each is preceded by at least one ?0? bit, are received with time difference of an integer number of 1 sec between two consecutive ?1? bit, then the cs flag in ssr equals ?1?. basically, the bb counts ?0? to ?1? transits on data_io input, where the time difference between two transits should be an integer number ( 2) of 1 sec. the number of consecutive ?1? bit that conforms to this rule is counted in the following example (figure 8-2) in one_cnt counter. one_cnt is incremented only if a ?1? bit that comes after a ?0? bit is received, where the time gap between the ?1? bit and the preceding ?1? bit is as mentioned above. if the time difference between two consecutive ?1? bit is out of the allowed deviation, the one_cnt is reset. one_cnt is also reset if the number of consecutive ?0? exceeds (csr (4:7) * 2) + 2, where csr is the last ?1? bit received is counted in zero_cnt. zero_cnt is reset each time ?1? bit is received. both m and n values are determined in csr register (csr (7:4) and csr (3:0) accordingly).
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 51 (this specification is subject to change without further notice) search window search window search window 1usec 1usec 2 * 1usec 1usec 1usec data_io signal (0) one_cnt=0 zero_cnt=1 (1) one_cnt=1 zero_cnt=0 (2) one_cnt=1 zero_cnt=1 (3) one_cnt=2 zero_cnt=0 (4) one_cnt=2 zero_cnt=0 (5) one_cnt=2 zero_cnt=1 (6) one_cnt=1 zero_cnt=0 fig. 8-4 carrier-sense example in the example shown in figure 8-2, at time (1) a new ?1? bit is received after a ?0? bit was received. thus, one_cnt equals 1 and zero_cnt is reset to 0. at time (2), a zero bit is received, so the zero_cnt is incremented. at time (3), a ?1? is received after a ?0? bit that was received before it. thus one_cnt is incremented and zero_cnt is reset. at time (4) a ?1? bit is received after a ?1? bit, thus, there is no change in any counter. at time (6) a ?1? bit is received out of the allowed window, so one_cnt is reset to 1. the csr register is used to configure the carrier-sense algorithm sensitivity. the csr register determines the number of ?1? bit required in order to decide that a carrier exists. the csr also determines the number of successive ?0? bits that reset the carrier-sense state machine. in ssr register, bit cs notifies whether a carrier was identified. carrier-sense can also be used as an interrupt. when cs in ssr goes from ?1? to ?0? i.e. the transmission has stopped, a cs interrupt is invoked (if enabled in ier). the purpose of this interrupt is to inform the mcu that the channel is free again. if the bb identifies a packet, the carrier-sense algorithm halts. when the bb is in rx mode and the lock flag in ssr is ?0?, the cs mechanism is working. when the lock flag in ssr is ?1?, the cs mechanism is not working, since the cs flag does not add any information because a preamble was identified already. after a preamble was identified the cs in ssr equals ?1?. 8.2.13 receiver reference capacitor discharge bb implements two independent mechanisms for receiver capacitor discharge: at the end of each received packet. zero counter. mechanism 1 is enabled/disabled by bit en_cap_disch in scr3. mechanism 2 is enabled/disabled by bit en_zero_disch in scr3.
EM77950 bb controller 52 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) the number of ?0? bits that will cause a discharge in mechanism 2 are determined by bits zero_disch_cnt [0:2]. for both mechanisms, the discharge time is determined by cap_dis_period in scr3. discharge is done by setting rx_tx pin to ?1? for a certain time and then setting it back to ?0?. (*) more detailed explanations of the reference capacitor discharge algorithms and motivations are can be found in the ?rfw - capacitor discharge.pdf? document. 8.2.14 changing bb configuration it is not recommended to change the bb configuration while it is in the middle of receiving or transmitting a packet. thus, before writing to any of the bb control registers (such as blr, pre-l, pre-h, ppr etc), do thefollowing: 1. change tx_rx mode to rx. 2. disable preamble search (search_en in scr2) 3. stop all rx receiving ? rx_stop. it is then safe to change the bb configuration. 8.2.15 input synchronizer handling asynchronous inputs to the bb. q q set clr s r q q set clr s r asynchronous input clk synchronized input 8.3 register description the registers in the bb are divided into three groups: ? read-only registers. mainly status registers. ? write-only registers. mainly control registers. ? read and write registers. in case of an rst pulse, all register are set to their default value.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 53 (this specification is subject to change without further notice) 8.3.1 bit length register (blr) this register is both a read and a write register. it determines the length of the bit in terms of clock cycles. the bit length will be (blr+6) clocks, since the minimum length of a bit is 6 clocks. default value: 00 (0+6=6). 8.3.2 preamble low register (pre-l) this register is a write-only register. this register contains the 8 least significant bits of the preamble. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pre-l pr-7 pr-6 pr-5 pr-4 pr-3 pr-2 pr-1 pr-0 default value: 0xeb. 8.3.3 preamble high register (pre-h) this register is a write-only register. this register contains the 8 most significant bits of the preamble. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pre-h pr-15 pr-14 pr-13 pr-12 pr-11 pr-10 pr-9 pr-8 default value: 0xff. 8.3.4 packet parameter register (ppr) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ppr net id_en node id_en fixed crc1 crc0 rb-2 rb-1 rb-0 this is a read and a write register. it contains control bits of the transmitted and received packet structure. default value: 0x3a.
EM77950 bb controller 54 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) bits 0-2 (rb-0~rb-2): refresh bits these bits determine the maximum number of successive ?zero? bytes allowed before an added ?one? bit is stuffed to the packet by the transmitter state machine. the reason for this feature is to keep the rfw-102 reference capacitor charged. refresh bit bit 2 bit 1 bit 0 refresh bit is added to every byte. 0 0 0 refresh bit is added if 1 byte equals x?00?. 0 0 1 refresh bit is added if 2 successive bytes equal x?00?. 0 1 0 refresh bit is added if 3 successive bytes equal x?00?. 0 1 1 refresh bit is added if 4 successive bytes equal x?00?. 1 0 0 refresh bit is added if 5 successive bytes equal x?00?. 1 0 1 refresh bit is added if 6 successive bytes equal x?00?. 1 1 0 refresh bit is added if 7 successive bytes equal x?00?. 1 1 1 the value of the refresh bit is determined by the value of the reference capacitor. bits 3, 4: crc [0:1] these bits control the crc operation for both transmit and receive mode: crc bit 4 bit 3 no crc 0 0 crc8 0 1 crc8 1 0 crc16 1 1 bit 5: fixed this controls the packet mode when high system packets are fixed size and the length is specified in the packet size register (psr). when fixed is low, the packet size is variable. the size is specified in the header of the incoming or outgoing packets. the location of the packet size field is specified in the lcr register. bit 6: node_id_en this is node_id control bit. 0 : disables node id search. 1 : enables node id search according to lcr, bir.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 55 (this specification is subject to change without further notice) bit 7: net_id_en this is net_id control bit. 0 : disables net id search. 1 : enables net id search according to lcr, nir. 8.3.5 system control register1 (scr1) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n/a n/a n/a n/a n/ a n/a n/a n/a n/a this byte is reserved. default value: 0x00. 8.3.6 system control register 2 (scr2) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scr2 pre mask 2 pre mask 1 pre mask 0 sto p rx tx fifo reset rx fifo reset search en tx_rx this register is a read and a write register. this register controls the system operation modes. bit 0: tx_rx controls the transceiver mode: receive mode or transmit mode when tx_rx is low ? bb is in receive mode (default mode). the output pin rx_tx is set to ?0?. bb searches for a preamble. if preamble is found, it handles the process of receiving a packet. if scr3 (7) is set, then the bb goes to rx mode and the output pin rx_tx is tx mode. the capacitor discharge can change the output pin rx_tx to tx mode even if we are in rx mode in the bb. in this case the output pin rx_tx will be in tx for a short duration and then return to rx mode. when tx_rx is high ? bb is in transmit mode. the output pin rx_tx is set to ?1?. bb handles the process of transmitting a packet according to the data in the tx_fifo. when it finishes transmitting the packet, it automatically goes back to receive mode.
EM77950 bb controller 56 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) bit 1: search_en preamble search enable bit. when 1 : enables the search for preamble in receive mode. when 0 : disables the search for preamble in receive mode, (used when user configures the system while in default receive mode). this bit?s default value is ?0?. it must be set to ?1? in order to start receiving a packet. bit 2: rx_fifo_reset this bit resets the rx_fifo address pointers when set to logic 1. this bit is set by mcu and is cleared automatically by bb. bit 3: tx_fifo_reset this bit resets the tx_fifo address pointers when set to logic 1. this bit is set by mcu and is cleared automatically by bb. bit 4: stop_rx this bit stops receiving the current command, resets the rx_fifo counters and start new searches for preamble. this bit is set by mcu and is cleared automatically by bb. bits 5-7: pre_mask [0:2] these bits determine the mask on pre-h in preamble correlation. meaning, it determines the size of the preamble in the receiver. the pre-l is always used in the preamble correlation. bb cuts off bit from pre-h register, starting from the msb. pre mask 0 pre mask 1 pre mask 2 preamble size 0 0 0 16 0 0 1 15 0 1 0 14 0 1 1 13 1 0 0 12 1 0 1 11 1 1 0 10 1 1 1 9 default value: 0x60
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 57 (this specification is subject to change without further notice) 8.3.7 system control register 3 (scr3) this register is a read and a write register. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scr3 low mode zero disch cnt 2 zero disch cnt 1 zero disch cnt 0 en zero disch. cap dis period en cap disch. - bit 1: en_cap_disch enables/disables capacitor discharge mechanism after each received packet: 0 : disables discharge. 1 : enables discharge. this bit overrides bit 3. bit 2: cap_dis_period determines the capacitor discharge duration: 0 : the pulse width is 36 clocks, (3 sec at 12 mhz clock). 1 : the pulse width is 72 clocks, (3 sec at 24 mhz clock). bit 3: en_zero_disch enables/disables zero counter mechanism for capacitor discharge: 0 : disables discharge 1 : enables discharge bits 4-6: zero_disch_cnt [0:2] determine the number of zero bits that will trigger a capacitor discharge by the zero counter mechanism. zero disch cnt 0 zero disch cnt 1 zero disch cnt 2 number of zeros 0 0 0 5 0 0 1 10 0 1 0 15 0 1 1 20 1 0 0 25 1 0 1 30 1 1 0 35 1 1 1 40
EM77950 bb controller 58 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) bit 7: low_mode enables or disables low power mode for rfw-102 0 : disables low mode (normal mode). 1 : enables low mode. bb is in rx mode, while rfw-102 is in tx mode. user has to put the bb into rx mode to disable rx and preamble search, before enabling low_mode. this transfers the rfw-102 to tx mode using rx_tx pin, while the bb is still in rx mode. rfw-102 power consumption is lower in tx mode than in rx mode. bb cannot remain in tx mode, if it is not transmitting. the low mode is the combination of both of the above. default value: 0x01 8.3.8 system control register 4 (scr4) this register is a read and a write register. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scr4 n/a n/a n/a n/a fifo flags win cont rf_ac tive ie bit 0: ie this flag enables all interrupts when set to ?1?. when ?0? all interrupts are disabled. bit 1: rf_active this bit controls rf_active pin. when th is bit is high the rf modem is active. bit 2: win cont this bit determines the size of the window in the preamble search module. if (blr+6) > 14 and win_cont=1, then the preamble window size is 5 bit 3: fifo flags determines the rx_fifo af flag and tx_fifo ae flag: if fifo flags = 0 then af = 12 and ae = 4. if fifo flags = 1 then af = 8 and ae = 8. default value: 0x00.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 59 (this specification is subject to change without further notice) 8.3.9 transmit fifo status register (tfsr) this register is a read-only register. it contains the number of bytes in the tx_fifo. default value: 0x00 (tx_fifo empty). 8.3.10 receive fifo status register (rfsr) this register is a read-only register. it contains the number of bytes in the rx_fifo. default value: 0x00 (tr_fifo empty). 8.3.11 location control register (lcr) this is a read and a write register. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lcr - size loc 2 size loc 1 size loc 0 net loc1 net loc 0 node loc 1 node loc 0 bits 0, 1: node_loc [0:1] these bits determine the location of the node_id parameter in the header (the location is specified in bytes excl uding preamble). the location should be fixed for all of different kinds of packets transferred by the system. node_id must never be set to be smaller than net_id, if both filters are enabled. location node loc 1 node loc 0 2 0 0 3 0 1 4 1 0 5 1 1 bits 2, 3: net_loc [0:1] these bits determine the location of the net_id parameter in the header (the location is specified in bytes excluding the preamble). the location should be fixed for all the different kinds of packets transferred by the system. location net loc 1 net loc 0 1 0 0 2 0 1 3 1 0 4 1 1
EM77950 bb controller 60 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) bits 4-5: size_loc [0:2] these bits determine the location of the packet size parameter in the header (the location is specified in bytes excluding the preamble). the location should be fixed for all the different kinds of packets transferred by the system. location size loc 2 size loc 1 size loc 0 2 0 0 0 3 0 0 1 4 0 1 0 5 0 1 1 6 1 0 0 7 1 0 1 8 1 1 0 9 1 1 1 default value: 0x00 8.3.12 node identity register (bir) this is a read and a write register. when the receiver state machine builds the incoming packet, it compares the value in the bir register to the received data at the location specified in lcr. if received node_id and the expected node_id are not equal, the packet is discarded. four multicast node_id addresses are implemented ?111111xx?. all packets whose 6 msbs are ?1? are not discarded. default value: 0x00 8.3.13 net identity register (nir) this is a read and a write register. when the receiver state machine builds the incoming packet, it compares the value in the nir to the received data at the location specified in lcr. if received net_id and the expected net_id are not equal, the packet is discarded. default value: 0x00
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 61 (this specification is subject to change without further notice) 8.3.14 system status register (ssr) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssr - tx_uf bit_error lock cs tx empty locked crc error this register is a read-only register. this register provides status information to the mcu concerning the communication line and the data transfer. bits 1, 2, 3 can trigger the interrupt if enabled in the ier. bits 0, 5 and 6 are set by h/w and cleared automatically after the mcu reads the register. bits 1~4 are set and cleared by h/w. bit 0: crc_error this flag indicates a crc error in the packet. the crc block sets this flag at the end of each received packet according to the crc calculation result. bb compares the calculated crc and the received crc. when these values differ, the flag goes high. the flag is cleared only after the mcu reads the ssr register. if the mcu does not read the ssr register, this flag remains ?1?. bit 1: locked this flag indicates that a packet is being received. bit 1 is set to logic 1 whenever the system identifies a new incoming packet (triggers lock in interrupt). the bit will reset to logic 0 when the packet ends (triggers lock out interrupt) or when one of the ids fails (net or byte). this indicator is important whenever we want to switch to transmit mode because it can tell us that the line is busy and that in most cases the transmission will not succeed. the lock triggers interrupt for every change in the bit status. bit 2: tx_empty this bit is the transmitter empty flag. when this bit is high the system is available for loading the next packet for transmission and bb is in receive mode. when the flag is low, bb is in the middle of a packet transmission. when transmitting few successive packets, the mcu should wait to the end of a packet before it reloads the tx_fifo with the next packet. bit 3: cs carrier sense detection bit when this bit is high, the system has identified a structure of packet transmission in the air according to csr. when low, no carrier has been detected. this bit is only valid in receive mode. the conditions for setting or clearing this flag are determined in the cs register. when locked is high, then cs is meaningless.
EM77950 bb controller 62 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) bit 4: lock this signals whether a preamble was identified or is still searching. when the flag is ?0?, the receiver is searching for preamble. when the flag is ?1? a preamble was identified. if a packet was discarded for any reason, the lock flag goes to 1. bit 5: bit_error this flag indicate that there was some error in the received package. the packet was not received according the expected timing specifications. the packet can still pass crc verification. bit 6: tx_uf this flag is set whenever the mcu reads a byte from an empty tx_fifo. this flag indicates abnormal end of packet transmission. the mcu transmitter?s state machine has expected to find a valid byte in the tx_fifo according to the packet size, but it found an empty tx_fifo. when this event occurs, the tx_empty interrupt is invoked and tx_uf (underflow) flag is set to ?1?. this flag is set by hardware and cleaned by mcu. it is cleaned whenever the mcu read the ssr register. default value: 0x04. 8.3.15 packet size register (psr) this is a read and a write register. it contains the packet size in byte units. when working in fixed size packets (see control bit-1), the size will be fixed for all types of packets. the size in psr excludes 2 bytes of preamble and 2, 1 or 0 bytes of crc. default value: 0x00. 8.3.16 carrier sense register (csr) this is both a read and a write register. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 csr zero cnt.3 zero cnt.2 zero cnt.1 zero cnt.0 one cnt.3 one cnt.2 one cnt.1 one cnt.0 bits 0-3: one_cnt [0:3] the number of successive ?1? bits that set the carrier sense high. bits 4-7: zero_cnt [0:3] the number of successive ?0? bits that reset the carrier sense (cs=?0?). default value: 0x44
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 63 (this specification is subject to change without further notice) 8.4 interrupt registers 8.4.1 interrupt enable register (ier) this register is a write and a read register. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ier cs tx_ae rx af tx empty rx_of link_ dis lock out lock in default value: 0x00. for all flags in this register, 0 : disable 1 : enable bit 0: lock_in this flag enables/disables the lock in interrupt. preamble + node_id + net_id identified correctly triggers lock in interrupt. bit 1: lock_out this flag enables/disables the lock out interrupt. end of received packet triggers lock_out interrupt. bit 2: link_dis this flag enables/disables the link_dis interrupt. the zero counter capacitor discharge triggers the link_dis interrupt. bit 3: rx_of this flag enables/disables the rx_of interrupt. end of received packet triggers rx_of interrupt. bit 4: tx_empty this flag enables/disables the tx_empty (transmitter empty) interrupt. x_empty interrupt tells the mcu that the transmitter has just finished transmitting a packet. bb goes to rx mode after finishing the transmission of a packet. bit 5: rx_af this flag enables/disables the rx_af interrupt. the rx_af interrupt is triggered when rx_fifo af flag goes from ?0? to ?1?. bit 6: tx_ae this flag enables/disables the tx_ae interrupt. the tx_ae interrupt is triggered when tx_fifo ae flag goes from ?0? to ?1?.
EM77950 bb controller 64 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) bit 7: cs this flag enables/disables the cs interrupt. cs flag in ssr negative edge triggers cs interrupt. 8.4.2 interrupt identification register (iir) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iir cs tx ae rx af tx empty rx_of link_ dis lock out lock in this is a read only register. when the mcu accesses the iir, all interrupts freeze. while the mcu access is occurring, the system records the changes in the interrupts but waits until the mcu access is complete before updating the register. a flag is active only when the matching interrupt enable bit is set, and does not depend on the ie bit value. the flags are set by h/w and cleared after the mcu reads the register. bit 0: this bit reflects the lock in flag interrupt when enabled by ier. this bit reflects the lock in flag interrupt when enabled by ier. lock_in interrupt is invoke whenever a preamble+net_id+node_id where recognized. if net_id is disabled, then a received preamble+ node_id invokes the interrupt. if node_id is disabled, then a received preamble+ net_id invokes the interrupt. if net_id and node_id are disabled, then a received preamble invokes the interrupt. bit 1: this bit reflects the lock out flag interrupt when enabled by ier. this bit reflects the lock out flag interrupt when enabled by ier. lock_out interrupt is invoked whenever rfw-d100 has finished receiving a packet. the end of the packet is determined according to the packet size. bit 2: this bit reflects the link_dis flag interrupt when enabled by ier. this interrupt is invoked by the zero counter capacitor discharge mechanism. bit 3: this bit reflects the rx_of flag interrupt when enabled by ier. bit 4: this bit reflects the tx empty flag interrupt when enabled by ier. bit 5: this bit reflects the rx fifo af flag interrupt when enabled by ier. bit 6: this bit reflects the tx fifo ae flag interrupt when enabled by ier. bit 7: cs ? when cs flag goes from ?1? to ?0?, an interrupt is invoked.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 65 (this specification is subject to change without further notice) 8.5 list of bb register mapping register address write read default values 0 (00000) tx_fifo rx_fifo ? ? 1 (00001) pre_l 0xff 2 (00010) pre_h 0xff 3 (00011) frc_l 0xff 4 (00100) frc_h 0xff 5 (00101) scr1 0x00 6 (00110) scr2 0x60 7 (00111) scr3 0x01 8 (01000) scr4 0x00 9 (01001) lcr 0x00 10 (01010) bir 0x00 11 (01011) nir 0x00 12 (01100) psr 0x00 13 (01101) ppr 0x3a 14 (01110) blr 0x00 15 (01111) csr 0x44 16 (10000) ier 0x00 17 (10001) ? iir ? ? 18 (10010) ? ssr ? 0x04 19 (10011) ? tfr ? 0x00 20 (10100) ? rfr ? 0x00 8.6 mcu bb control registers 8.6.1 control registers list rfaar (0x2d): register r2d indicates wm indirect ram address. rfdb (0x2e): register r2e indicates wm indirect ram data. rfacr (0x2f): register r2f indicates wm ram access control. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - - rrst rfrd rfwr rfintf (0x30): bb interrupt flags. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 csdf tx_aef rx_aff tx_ emptyf rx_off link_ disf lock_ou tf lock_ inf
EM77950 bb controller 66 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) rfinte (0x99): bb interrupt enable. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 csde tx_aee rx_afe tx_ emptye rx_ofe link_ dise lock_ou te lock_ ine prie (0x80): peripherals enable control. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spie - bbe ade pwm1e pwm0e tcce frce 8.6.2 bb control example org 0x0060 // tx_empty int address bc rfintf, tx_emptyf // rf data send out, clear int flag. reti org 0x0100 start: bs rfacr, rrst // bb reset. nop bc rfacr, rrst bs prie, wme // bb power enable. mov a, #0x10 mov rfinte, a // bb int.tx_empty enable. eni // enable all int. rf_tx_initial: write #scr2, #8 // reset tx_fifo, rx mode. write #blr, #10 // set bit rate. write #ppr, #33 // set package size to be fixed. // refresh bit mode 1. crc disabled write #psr, #6 // set package size to 6. write #pre_h, #0xdc // set preamble high byte value. write #pre_l, #0xa7 // set preamble low byte value. rf_send_data: write #tx_fifo, #0x01 // write first byte of package to // tx_fifo. write #tx_fifo, #0x02 write #tx_fifo, #0x03 write #tx_fifo, #0x04 write #tx_fifo, #0x05 write #tx_fifo, #0x06 // write last byte of package to // tx_fifo. read #tfr, 0x60 // read tfr register data write #ier, #16 // enable tx_empty int write #scr4, #0x03 // enable all int. write #scr2, #1 // move from rx to tx mode.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 67 (this specification is subject to change without further notice) loop: jmp loop write_data_to_rf: // bb register write sub bc rfacr, rfwr nop nop bs rfacr, rfwr ret read_data_from_rf: // bb register read sub nop nop nop nop bc rfacr, rfrd nop nop nop nop nop // note the access time mov a, rfdb nop nop nop bs rfacr, rfrd ret ; =============================================== write macro#con1, #con2 // bb register write macro mov a, #con2 mov rfdb, a mov a, #con1 mov rfaar, a call write_data_to_rf endm ; =============================================== readmacro#con, reg // bb register read macro mov a, #con mov rfaar, a call read_data_from_rf mov reg, a endm
EM77950 bb controller 68 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 9 direction serial peripheral interface (spi) 9.1 introduction the EM77950 communicates with other devices via spi (direction serial peripheral interface) module, as shown in fig. 9-1. to accomplish communication, spi uses three wire synchronous protocols: serial clock, serial data output, and serial data. if the EM77950 is a master controller, it sends clock through the sck pin. an 8-bit data is transmitted and received at the same time. if the EM77950, however, is defined as a slave, its sck pin could be programmed as an input pin. data will continue to be shifted on the basis of both the clock rate and the selected edge. 9.2 features ? 3-wire, full duplex synchronous transceiver ? operation in either master mode or slave mode ? programmable baud rates of communication ? programming clock polarity ? programmable data transmission order ? interrupt flag available for read buffer full ? up to 8 mhz (maximum) bit frequency 9.3 block diagram read buffer (spirb) write buffer (spiwb) shift register (spis) clock generator read buffer (spirb) write buffer (spiwb) shift register (spis) clock generator spi master spi slave sdo sdo sck sck sdi sdi fig. 9-1 typical spi transceiver mode
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 69 (this specification is subject to change without further notice) 9.4 transceiver timing spie sck ces = 1 sdo sdod = 0 sdi sdid = 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit 6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bi t 6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 sck ces = 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sdo sdod = 1 bit 6 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bi t 6 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 sdi sdid = 1 rbf fig. 9-2 spi transceiver timing 9.5 related registers with spi as the spi mode is defined, the related registers of this operation are shown below: spirb (0x1d): serial peripheral interface read register spiwb (0x1e): serial peripheral interface write register intf (0x11): interrupt flag bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adif rbfif pwm1if pwm0if eint1f eint0f tccof frcof prie (0x80): peripherals enable control bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spie - bbe ade pwm1e pwm0e tcce frce inte (0x81): interrupt enable control bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gie rbfie pwm1ie pwm0ie eint1e eint0e tccoe frcoe spic (0x85): spi control. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spi_rbf ces sbr2 sbr1 sbr0 sdid sdod spis
EM77950 bb controller 70 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 9.6 function description 9.6.1 block diagram description the following subsections describe the function of each blocks and signals. fig. 9.2 depicts how the spi communication is carried out. sdi: serial data in sck: serial clock sdo: serial data out rbfif: set by buffer full detector, and reset by software spis: loads the data in spiwb register, and begin to shift shift reg.: shifting byte out and in. the order is defined by bit sdod. both the shift register and the spiwb registers are loaded at the same time. once data are written to, spis starts transmission / reception. the received data will be moved to the spirb register, as the shifting of the 8-bit data is completed. the rbfif (read buffer full) flag is equal to 1. spirb: read buffer. the buffer will be updated, as the 8-bit shifting is completed. the data must be read before the next reception is finished. the rbf flag is cleared as the spirb register is read. spiwb: write buffer. the buffer will deny any write until the 8-bit shifting is completed. the spis bit will be kept in 1 if the communication is still undergoing. this flag must be cleared as the shifting is finished. users can determine if the next write attempt is available. sbr2~sbr0: programming the clock frequency/rates and sources. edge select: selecting the appropriate clock edges by programming the ces bit. 9.6.2 signal & pin description the three pins, sdi, sdo, and sck, which are shown in fig. 9-1, will be explained in details as follows: sdi: ? sdi: serial data in ? serial data in ? receive serially ? defined as high-impedance, if not selected.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 71 (this specification is subject to change without further notice) ? programmed the same clock rate and the same clock edge to latch on both the master device and slave device. ? the received byte will replace the corresponding transmitted byte. ? the rbfif bit will be set, as the spi operation is completed. ? timing is shown in fig. 9-2. sck: ? serial clock. ? generated by a master device. ? synchronize the data communication on both the sdi pin and the sdo pin. ? the ces used to select the edge to communicate. ? the sbr0~sbr2 used to determine the baud rate of communication. ? the es, sbr0, sbr1, and sbr2 bit have no effect in the slave mode. ? timing is shown in fig. 9-2 sdo: ? serial data out ? transmit serially ? programmed the same clock rate and the same clock edge to latch on both the master device and slave device. ? the received byte will replace the transmitted byte. ? the spis bit will be reset, as the spi operation is completed. ? timing is shown in fig. 9-2. 10 analog to digital converter (adc) the analog-to-digital circuitry consists of one 16-to-1 multiplexer, two control registers (adcais and adccr), one data register (addata) and one adc calculator with 8-bit resolution. the functional block diagram of the adc is shown in fig. 10. port d [7:0] and port e [7:0] can be selected as either normal digital i/o ports or analog input ports. a maximum of 16 analog input pins can be selected by adcais register [5:3], ims3 ~ims0 bits. control bits, aips3 ~ aips0, of adccr [3:0] are then used to select the adc input channel that will supply analog signal to adc calculator. ckr2 ~ ckr0 control bits are used to select the desired conversion rate. the adc module, then, utilizes successive approximation to convert the unknown analog signal into an 8-bit digital output value. finally, the 8-bit result is fed to the addata register. if the adc interrupt is enabled, the adc interrupt flag will be set to ?1? as the analog-to-digital conversion is completed.
EM77950 bb controller 72 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 2 0 1 2 0 1 5 3 4 addata data bus adc4 adc3 adc2 adc0 adc5 adc6 adc7 adc8 vref power down fsco 7 8-1 mux adc ( successive approximation ) 7 16 -1 analog switch ckr[0:2] ims[0:2] aips[0:3] start to convert adc9 adca adcb adc1 3 7 6 adrun 4 3 4 5 ade adif 2 ade 1 0 adcc adcd adce adcf fig.10 analog-to-digital conversion functional block diagram 10.1 adc control registers as the adc mode is defined, the related registers of this operation are shown below: intf (0x11): i nterrupt flag, bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adif rbfif pwm1if pwm0if eint1f eint0f tccof frcof addata (0x1f): adc 8-bit data. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 add7 add6 add5 add4 add3 add2 add1 add0 when the a/d conversion is completed, bit 7 ~ bit 0 are loaded to the addata [7:0]. the adcrun bit is cleared, and the adif is set. prie (0x80): peripherals enable control bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spie - bbe ade pwm1e pwm0e tcce frce adcais (0x96): adc analog input pin select and conversion rate select. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - ims2 ims1 ims0 ckr2 ckr1 ckr0
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 73 (this specification is subject to change without further notice) ims2~ims0 (bit 2 ~ bit 4): adc configuration definition bit. ims pte 7 pte 6 pte 5 pte 4 pte 3 pte 2 pte 1 pte 0 ptd 7 ptd 6 ptd 5 ptd 4 ptd 3 ptd 2 ptd 1 ptd 0 adc f e d c b a 9 8 7 6 5 4 3 2 1 0 000 a a d d d d d d d d d d d d d d 001 a a a a d d d d d d d d d d d d 010 a a a a a a d d d d d d d d d d 011 a a a a a a a a d d d d d d d d 100 a a a a a a a a a a d d d d d d 101 a a a a a a a a a a a a d d d d 110 a a a a a a a a a a a a a a d d 111 a a a a a a a a a a a a a a a a ckr2~ckr0 (bit 2 ~ bit 0): ad conversion rate control bits. a/d conversion rate unit: khz ckr2: ckr1: ckr0 divided rate 6mhz clock source 12mhz clock source 24mhz clock source 48mhz clock source 000 2 250 500 1000 2000 001 4 125 250 500 1000 010 8 62.5 125 250 500 011 16 31.3 62.5 125 250 100 32 15.6 31.3 62.5 125 101 64 7.8 15.6 31.3 62.5 110 128 3.9 7.8 15.6 31.3 111 256 2.0 3.9 7.8 15.6 adccrr (0x97): adc configuration register. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adrun adie - - aips3 sipa2 aips1 aips0 aips0~aips3 (bits 0~3): analog input select. 0000 = an0;0001 = an1; 0010 = an2;0011 = an3 0100 = an4;0101 = an5; 0110 = an6;0111 = an7 1000 = an8;1001 = an9; 1010 = ana;1011 = anb 1100 = anc;1101 = and; 1110 = ane;1111 = anf they can only be changed when the adif bit and the adrun bit are both low.
EM77950 bb controller 74 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) adie (bit 6) : adc interrupt enable. adrun (bit 7) : adc starts to run 0 = reset on completion of the conversion; this bit cannot be reset by software. 1 = an a/d conversion is started; this bit can be set by software. 10.2 programming steps/considerations follow these steps to obtain data from the adc: 1. set adc function power on (prie.ade). 2. write to the three bits (ims2:ims0) on the adccr register to define the characteristics of pd and pf: digital i/o, analog channels, and voltage reference pin; 3. write to the adcais register to configure adc module: i select adc input channel (aips3: aips0) ii define adc conversion clock rate (ckr2: ckr1: ckr0) 4. set adc interrupt enable (adccr.adie). include the ?eni? instruction, if the interrupt function is employed. 5. set the adrun bit to 1 to begin sampling. 6. wait for either the interrupt flag to be set or the adc interrupt to occur. 7. read the conversion data register addata. 8. clear the interrupt flag bit (intf.adif). 9. for next conversion, go to step 2 or step 3 as required. at least 2tct is required before the next acquisition starts. note to obtain an accurate value, it is necessary to avoid any data transition on the i/o pins during ad conversion.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 75 (this specification is subject to change without further notice) 11 dual pulse width modulations (pwm0 and pwm1) 11.1 overview the EM77950 has two built-in pwm outputs with 16-bit resolution. fig.11-1 shows the functional block diagram. a pwm output has a period and a duty cycle, and it keeps the output high. the baud rate of the pwm is the inverse of the period. fig. 11-2 depicts the relationships between a period and a duty cycle. duty compare circuit period circuit q s r pwm1 data bus pwm1if pwm0if duty compare circuit period compare circuit q s r pwm0 tmr0hb tmr0lb prd1h prd1l tmr1hb tmr1lb dt1h dt1l set as compare match set as compa re match set as compare match set as compare match compare q s r pwm1ie duty compare circuit pwm0ie dl1l dl1h dl0h dl0l dt0h dt0l prd0h prd0l mux fosc/2 mux fosc/2 pwm1e s_pwm0 s_wmp1 pwm0e pwm0e pwm1e fig. 11-1 the functional block diagram of the dual pwm period period period duty duty duty duty = tmr prd= tmr fig. 11-2 pwm output timing diagram
EM77950 bb controller 76 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 11.2 pwm control registers as the pwm mode is defined, the related registers of this operation are shown below: intf (0x11): interrupt flag bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adif rbfif pwm1if pwm0if eint1f eint0f tccof frcof dt0l (0x21): duty of pwm0 low byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dt07 dt06 dt05 dt04 dt03 dt02 dt01 dt00 dt0h (0x22): duty of pwm0 high byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dt0f dt0e dt0d dt0c dt0b dt0a dt09 dt08 dl0l (0x25): duty latch of pwm0 low byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dl07 dl06 dl05 dl04 dl03 dl02 dl01 dl00 dl0h (0x26): duty latch of pwm0 high byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dl0f dl0e dl0d dl0c dl0b dl0a dl09 dl08 dt1l (0x27): duty of pwm1 low byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dt17 dt16 dt15 dt14 dt13 dt12 dt11 dt10 dt1h (0x28): duty of pwm1 high byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dt1f dt1e dt1d dt1c dt1b dt1a dt19 dt18 dl1l (0x2b): duty latch of pwm1low byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dl17 dl16 dl15 dl14 dl13 dl12 dl11 dl10 dl2h (0x2c): duty latch of pwm1 high byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dl1f dl1e dl1d dl1c dl1b dl1a dl19 dl18 the pwm duty cycle is defined by writing to the dtx register, and is latched from dtx to dlx while tmrx is cleared. when dlx is equal to tmrx, the pwmx pin is cleared. dtx can be loaded at any time. however, it cannot be latched into dlx until the current value of dlx is equal to tmrx.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 77 (this specification is subject to change without further notice) the following formula describes how to calculate the pwm duty cycle: duty cycle = (dtx+1) * (2/fosc) prd0l (0x23): period of pwm0 low byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 prd07 prd06 prd05 prd04 prd03 prd02 prd01 prd00 prd0h (0x24): period of pwm0 high byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 prd0f prd0e prd0d prd0c prd0b prd0a prd09 prd08 prd1l (0x29): period of pwm1 low byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 prd17 prd16 prd15 prd14 prd13 prd12 prd11 prd10 prd1h (0x2a): period of pwm1 high byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 prd1f prd1e prd1d prd1c prd1b prd1a prd19 prd18 the pwm period is defined by writing to prdx. when tmrx is equal to prdx, the following events occur on the next increment cycle: ? tmrx is cleared. ? the pwmx pin is set to 1. ? the pwmx duty cycle is latched from dtps to duty. note the pwmx will not be set, if the duty cycle is 0; ? the pwmxif pin is set to 1. ? the following formula describes how to calculate the pwm period: period = (prd +2) * (2/fosc) the function of pwm must be disabled before a new period being executed. in other word, bit pwmxe has to be reset by advance, if the contents of prdx are reloaded. prie (0x80): peripherals enable control bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spie - bbe ade pwm1e pwm0e tcce frce inte (0x81): interrupt enable control bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gie rbfie pwm1ie pwm0ie eint1e eint0e tccoe frcoe pwmcr (0x98): pwm control bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - s_pwm1 s_pwm0 - -
EM77950 bb controller 78 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 11.3 pwm programming procedures/steps (1) load prdx with the pwmx period. (2) load dtx with the pwmx duty cycle. (3) enable the interrupt function by setting pwmxie in the inte register, if required. (4) set the pwm pin as output by setting pwmcr.s_pwmx. (5) enable the pwm function by setting pwmxe bit in the prie register. (6) write the desired new duty to dtx before tmrx is equal to prdx, then this new dtx will be latched into dlx if various duty cycle is required for the next pwmx operation. (7) clear pwmxe bit and write the desired new period to prdx, then enable it again if various periods are required for the next pwmx operation. (8) clear the pwmxif before the next operation if interrupt pwmxie is employed. 12 interrupts 12.1 introduction the EM77950 has 15 interrupt sources. by priority, these interrupts are classified into two levels, namely; peripherals and base band, as described in the following: the interrupt status registers record the interrupt requests in the corresponding control bits in the interrupt control registers. the global interrupt (gie) is enabled by the eni instruction and is disabled by the disi instruction. the interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts. the flags in the interrupt status register are set regardless of the status of their corresponding mask bits or the execution of disi. note that the logic and of an interrupt flag and its corresponding interrupt control bit is 1 which makes the program counter point to the right interrupt vector. refer to fig. 12-1. the reti instruction ends the interrupt routine and enables the global interrupt (the execution of eni). before the interrupt subroutine is executed , the contents of acc, sr and romps will be saved by the hardware. after the interrupt service routine is finished, acc, sr and romps will be pushed back.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 79 (this specification is subject to change without further notice) in EM77950, individual interrupt sources have their own interrupt vectors, depicted in the following table: mnemonic mask status no mask status priority vector function register bit register bit 1 kwuae kwube kwuaif kwubif 1 0x10 key wake up 0x82 0x83 3~0 all 0x12 013 3~0 all 2 eint0e eint1e eint0f eint1f 1 0x18 external interrupt 0x81 2 3 0x11 2 3 3 frcoe frcof 1 0x20 frc overflow 0x81 0 0x11 0 4 tccoe tccof 1 0x28 tcc overflow 0x81 1 0x11 1 5 rbfie rbfif 1 0x30 read buffer full of spi 0x81 6 0x11 6 6 adcie adcif 1 0x38 adc complete 0x80 4 0x11 7 7 pwm0ie pwm1ie pwm0if pwm1if 1 0x40 pwm period complete 0x81 4 5 0x11 4 5 8 csde csdf 2 0x48 carrier sense interrupt 0x99 7 0x30 7 9 tx_aee tx_aef 2 0x50 tx fifo almost empty 0x99 6 0x30 6 10 rx_afe rx_aff 2 0x58 rx fifo almost full 0x99 5 0x30 5 11 tx_empty tx_emptyf 2 0x60 tx fifo empty 0x99 4 0x30 4 12 rx_ofe rx_off 2 0x68 rx fifo overflow 0x99 3 0x30 3 13 link_dis link_dis 2 0x70 link_dis interrupt 0x99 2 0x30 2 14 lock_oute lock_outf 2 0x78 lock out interrupt 0x99 1 0x30 1 15 lock_ine lock_inf 2 0x80 lock in interrupt 0x99 0 0x30 0 the interrupt priority is another useful feature provided by this ic. the latest interrupt, which has the highest priority than the others, will override and hold the currently executed interrupt until the interru pt is finished. otherwise, the latest interrupt will be in queue right after all its peers. function enable function int condition happened function int vector address function int flag function int enable global int enable fig. 12 block diagram of interrupts
EM77950 bb controller 80 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 13 circuitry of input and output pins 13.1 introduction the EM77950 has six parallel ports, namely port a, port b, port c, port d, port e and port f. there are 40 available i/o pins. a control bit defines the configuration of its corresponding pin. refer to fig. 3.1 for the pin assignment. the i/o registers, from port a to port f, are bidirectional tri-state i/o ports. the i/o ports can be defined as "input" or "output" pins by the i/o control registers (ioca, iocb, iocd, ioce and iocf) under program control. the i/o registers and i/o control registers are both readable and writable. 14 timer/counter system 14.1 introduction the EM77950 provides two timer modules: 8-bit tcc (timer clock/counter), and 16-bit frc (free run counter). the clock sources of tcc come from one of the instruction cycles and low frequency oscillator (irc). the clock source of frc is from either the instruction cycle or low frequency oscillator (irc). 14.2 time clock counter (tcc) an 8-bit counter is available as prescaler for the tcc. the prescaler ratio is determined by the ps0~ps2 bits. when in tcc mode, the prescaler is cleared each time an instruction writes to the tcc. ? tcc is an 8-bit timer/counter. if the tcc signal source is from the system clock, tcc will be incremented by 1 for every instruction cycle (without prescaler). ? if the tcc signal source is from the irc clock input, tcc will be incremented by 1 on every falling edge or rising edge of the tcc pin. ? the prescaler counter (prc) can be read from address 0x0f. in other words, the combination of tcc and prc can be used as a 16-bit counter without prescaler 14.2.1 block diagram of tcc m u x prc (8- bit counter) 8-1 mux tcc ps0 ps1 ps2 tccof data bus fosc 1 0 irc tcce sync with internal clock 2 clocks delay tccs0 fig. 14-1 function block diagram of tcc
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 81 (this specification is subject to change without further notice) 14.2.2 tcc control registers as the tcc mode is defined, the related registers involved in this operation are shown below: prc (0x0f): prescale counter. tcc (0x10): timer clock/counter. intf (0x11): interrupt flag. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adif rbfif pwm1if pwm0if eint1f eint0f tccof frcof prie (0x80): peripherals enable control bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spie - bbe ade pwm1e pwm0e tcce frce inte (0x81): interrupt enable control bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gie rbfie pwm1ie pwm0ie eint1e eint0e tccoe frcoe tccc (0x93): timer clock/counter control. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - tccs0 ps2 ps1 ps0 14.2.3 tcc programming procedures/steps (1) load tccc with the prescaler and tcc clock source. (2) load tcc with the tcc overflow period. (3) enable the interrupt function by setting tccoe in the inte register, if required. (4) enable the tcc function by setting the tcce bit in the prie register. (5) wait for either the interrupt flag to be set (tccof) or the tcc interrupt to occur. (6) the following formula describes how to calculate the tcc overflow period: () ? ? ? ? ? ? ? = e clocksourc escaler tcc timer tcc 1 pr 100 0 where clock source = fosc or irc
EM77950 bb controller 82 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 14.3 free run counter dual 8-bit counters, high byte register and low byte register, make up the 16-bit software programmable counter. the driving clock source is either the system clock divided by 2 or the low frequency oscillator. a read of the low byte register allows full control of the corresponding timer function. on the contrary , accessing a high byte register will inhibit the specific timer function until the corresponding low byte is read as well. 14.3.1 block diagram of frc m u x lfrf frcof data bus fosc 1 0 irc frce sync with internal clock frccs hfrc lfrfb fig. 14-2 function block diagram of timer 1 14.3.2 frc control registers as the frc mode is defined, the related registers of this operation are shown below: intf (0x11): interrupt flag. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adif rbfif pwm1if pwm0if eint1f eint0f tccof frcof lfrc (0x1a): least significant byte of 16-bit free run counter. hfrc (0x1b): most significant byte of 16-bit free run counter. lfrcb (0x1c): least significant byte buffer of 16-bit free run counter. prie (0x80): peripherals enable control bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spie - bbe ade pwm1e pwm0e tcce frce inte (0x81): interrupt enable control bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gie rbfie pwm1ie pwm0ie eint1e eint0e tccoe frcoe frcc (0x94): free run counter control. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - osco2e osco2sl1 osco2sl0 ppscl2 ppscl1 ppscl0 frccs
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 83 (this specification is subject to change without further notice) 14.3.3 frc programming procedures/steps (1) load lfrcb with the frc overflow period low byte. (2) load hfrc with the tcc overflow period high byte. then lfrc will load with the lfrcb automatically. (3) enable interrupt function by setting frcoe in the inte register, if required. (4) enable frc function by setting frce bit in the prie register. (5) wait for either the interrupt flag to be set (frcof) or the frc interrupt to occur. (6) an access of low byte of a 16-bit counter receives the count value at the moment of the read. however, the contents of low byte will transfer to the buffer, the lfrcb register, if a high byte is read first. the value in the lfrcb register remains unchanged until the corresponding low byte is read. (7) the following formula describes how to calculate the frc overflow period: () ? ? ? ? ? ? ? = e clocksourc lfrc hfrc timer frc 1 : 10000 0 where clock source = fosc or irc 15 reset and wake up 15.1 reset a reset can be caused by one of the following: (1) power-on reset (2) /reset pin input "low", or (3) watchdog timer time-out (if enabled) the device will remain in a reset condition for a period of 8-bit external rc ripple counter (one oscillator start-up timer pe riod) after the reset is detected. the initial address is 000h. 15.2 the status of rst, t, and p of the status register a reset condition can be caused by the following events: (1) a power-on condition (external); (2) a high-low-high pulse on the /reset pin (external); and (3) watchdog timer time-out (internal). the values of bits rst, t and p, listed in table 17.1 can be used to check how the processor wakes up.
EM77950 bb controller 84 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) table 17.1 values of rst, t and p after a reset condition rst t p power on 0 1 1 wdtc instruction * p 1 * p wdt timeout * p 0 * p slep instruction * p * p 0 wake-up on pin change during sleep mode 1 1 0 * p: previous status before reset 15.3 system set-up time (sst) in order to have a successful start up, system set-up time (ssu) is employed to guarantee a stable clock for ic operation. it is made up of two delay sources: (1) internal rc oscillation set-up delay (ircosud): internal rc oscillation shared with a watchdog timer divided by an 8-bit ripple counter. (2) main oscillation set-up delay (mosud): a 10-bit ripple c ounter is used to filter unstable main clocks at the beginning of power-on before the chip starts to run. this delay is performed right after ircosud, if enabled 10 8 2 1 2 768 . 32 1 ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = clock main k sst 8 - bit ripple counter internal rc osc . 10 - bit ripple counter osc1 rcsute sst fig. 15 system set-up time
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 85 (this specification is subject to change without further notice) 15.4 wake-up procedure on power-on reset power-on voltage detector (povd) will allo w the vdd whose value is over the default threshold voltage (2.0 v for the EM77950) to enter the ic, and the sst delay starts. the following three cases may be taken into consideration: (1) /reset pin goes high with vdd at the same time. in hardware, this pin and vdd are tied together. the internal reset will remain low until the sst delay is over. (2) /reset pin goes high during the sst delay. it is similar to case 1. the ic will start to operate when the sst delay is over. /reset pin goes high after an sst delay. the EM77950 will start program execution immediately 16 oscillators 16.1 introduction the EM77950 provides three main oscillat ors: one high frequency crystal oscillator (connected to osci and osco), internal rc, and four pll (phase lock loop) outputs. versatile combinations of oscillation are pr ovided for a wide range of applications. on-chip clock sources can be either dual clocks or single clock. 16.2 clock signal distribution frcc.frccs mcu kernel 8 bit adc 16 bit pwm 8 bit tcc wdt 6mhz irc clk 6 12 pll 24 48 pd (power down) byp sys_clk 0/1=0 & rf_clk 0/1=0 sys_clk 0/1 tccc.tccs0 sr.green sys_nclk sys_iclk spi rf-bb rf_clk 0/1 16 bit frc fig. 16 clock tours
EM77950 bb controller 86 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 16.3 pll oscillator the phase-locked loop (pll) technology is employed to produce four different frequencies: 6 mhz, 12mhz, 24mhz and 48 mhz (external 6mhz crystal). setting the sys_clk bits can select the system clock source. pll is enabled except when entering green and sleep mode. 16.4 selected pll oscillation out as shown in register frcc (0x94), EM77950 can output the selected pll frequency divided by the prescaler. once the pin is enabled as a pll clock out, the output frequency can be implemented by the peripherals of the chip. if disabled, this pin is used as pin pf0, a general purpose i/o pin. 17 low-power mode 17.1 introduction the EM77950 has two power-saving modes, green mode and sleep mode. figure 17 shows the mode change diagram. power on normal green sleep 1. wdtc[7].green=1 2. wdt time out 3. /reset 1. key wake-up 2. wdt time out 3. /reset slep inst. wdtc[7].green=0 slep inst. key wake up fig. 17 three-mode state
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 87 (this specification is subject to change without further notice) 17.2 green mode the ?green? bit of wdtc [7] register is the only control bit used for mode switching between normal mode and green mode. its initial value is ?0?, normal mode. when ?green? bit is written with a 1, the mcu will switch to green mode from normal mode. in contrast, the mcu will go back to normal mode when the ?green? bit is written from 1 to 0. during green mode, the main osc illator and pll will be turned off. the mcu and all the peripherals are driven by the internal rc oscillator - irc. once bb peripheral is functional and then switched into green mode, the clock source of all other peripherals, except pll, will be provided by irc. pll will keep running as bb circuit?s clock source. 17.3 sleep mode the execution of ?slep? instruction will turn the whole chip into sleep mode. the main clock will be shut down. the irc oscillator is halted also if the watchdog function is disabled. all registers, memory and i/o port remain in their previous states during sleep mode. the overflow of the watchdog timer driven by irc will generate a reset to resume normal operation. key wake up (kwu) interrupt and /reset pin are other methods to exit sleep mode. it is essential to wait for stable oscillation start-up time before normal operation. the stabilizing time is sst.
EM77950 bb controller 88 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 18 instruction description 18.1 instruction set summary type binary instruction mnemonic operation status affected cycles 0000 0000 0000 0000 nop no operation none 1 0000 0000 0000 0001 wdtc wdt 0 none 1 0000 0000 0000 0010 ret pc (top of stack) none 1 0000 0000 0000 0011 reti pc (top of stack); enable interrupt none 1 0000 0000 0000 0100 slep wdt 0 stop oscillator none 1 0000 0000 0000 0101 eni enable interrupt none 1 0000 0000 0000 0110 disi disable interrupt none 1 system control 0000 0000 0000 0111 daa decimal adjust a c 1 1010 0000 rrrr rrrr tbrdp r r rom[(tabpt[15:1])] tabpt tabpt+1 none 2 1010 0001 rrrr rrrr tbrd r r rom[(tabpt[15:1])] none 2 1010 0010 rrrr rrrr tbrdm r r rom[(tabpt[15:1])] tabpt tabpt-1 none 2 0000 0000 0000 1010 tbrdp a a rom[(tabpt[15:1])] tabpt tabpt+1 none 2 0000 0000 0000 1011 tbrd a a rom[(tabpt[15:1])] none 2 0000 0000 0000 1100 tbrdm a a rom[(tabpt[15:1])] tabpt tabpt-1 none 2 0011 1101 0000 0010 tbl r2 r2+a c, dc, z 1 table look up 1010 1011 kkkk kkkk retl #k a k pc [top of stack] none 1 0000 0001 rrrr rrrr or a, r a a .or. r z 1 0000 0010 rrrr rrrr or r, a r r .or. a z 1 0000 0011 kkkk kkkk or a, #k a a .or. k z 1 0000 0100 rrrr rrrr and a, r a a .and. r z 1 0000 0101 rrrr rrrr and r, a r r .and. a z 1 0000 0110 kkkk kkkk and a, #k a a .and. k z 1 0000 0111 rrrr rrrr xor a, r a a .xor. r z 1 0000 1000 rrrr rrrr xor r, a r r .xor. a z 1 0000 1001 kkkk kkkk xor a, #k a a .xor. k z 1 0000 1010 rrrr rrrr coma r a /r z 1 0000 1011 rrrr rrrr com r r /r z 1 1011 00kk rrrr rrrr rrca r, #k [c,r] rotate right k bits to [c,a] c 1 1011 01kk rrrr rrrr rrc r, #k [c,r] rotate right k bits to [c,r] c 1 1011 10kk rrrr rrrr rlca r, #k [c,r] rotate left k bits to [c,a] c 1 1011 11kk rrrr rrrr rlc r, #k [c,r] rotate left k bits to [c,r] c 1 0101 10kk rrrr rrrr shra r, #k [c,r] shift right k bits to a insert c into high order bits none 1 logic 0101 11kk rrrr rrrr shla r, #k [c,r] shift left k bits to a insert c into low order bits none 1
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 89 (this specification is subject to change without further notice) type binary instruction mnemonic operation status affected cycles 0001 xxaa 0bbb aaaa rrrr aaaa rrrr aaaa jbc r,b,addr if r(b)=0, jump to addr none 2/3 0001 xxaa 1bbb aaaa rrrr aaaa rrrr aaaa jbs r,b,addr if r(b)=1, jump to addr none 2/3 0101 xxaa 0010 aaaa rrrr aaaa rrrr aaaa djza r,addr a r-1, jump to addr if zero none 2/3 0101 xxaa 0011 aaaa rrrr aaaa rrrr aaaa djz r,addr r r-1, jump to addr if zero none 2/3 0101 xxaa 0100 aaaa rrrr aaaa rrrr aaaa jza r,addr a r+1, jump to addr if zero none 2/3 compare branch 0101 xxaa 0101 aaaa rrrr aaaa rrrr aaaa jz r,addr r r+1, jump to addr if zero none 2/3 0010 0bbb rrrr rrrr bc r,b r(b) 0 none 1 0010 1bbb rrrr rrrr bs r,b r(b) 1 none 1 0011 0bbb rrrr rrrr btg r,b r(b) /r(b) none 1 0011 1000 rrrr rrrr swap r r(0:3) ? r(4:7) none 1 0011 1001 rrrr rrrr swapa r a(4:7) r(0:3) a(0:3) r(4:7) none 1 1010 1100 rrrr rrrr zchk r z 0 if r < > 0 z 1 if r = 0 z 1 0000 0000 0000 1101 rpt single repeat cs times on next tbrd instruction none 1 process 1010 1111 rrrr rrrr clr r r 0 z 1 0011 1100 rrrr rrrr add a,r a a+r c, dc, z 1 0011 1101 rrrr rrrr add r,a r r+a c, dc, z 1 0011 1110 kkkk kkkk add a,#k a a+k c, dc, z 1 0100 0010 rrrr rrrr sub a,r a r-a c, dc, z 1 0100 0011 rrrr rrrr sub r,a f r-a c, dc, z 1 0100 0100 kkkk kkkk sub a,#k a k-a c, dc, z 1 0100 1110 rrrr rrrr inca r a r+1 c, dc, z 1 0100 1111 rrrr rrrr inc r r r+1 c, dc, z 1 0101 0000 rrrr rrrr deca r a r-1 c, dc, z 1 arithmetic 0101 0001 rrrr rrrr dec r r r-1 c, dc, z 1 1010 1000 rrrr rrrr mov a,r a r z 1 1010 1001 rrrr rrrr mov r,a r a none 1 0110 r2 r2 r2 r2 r2 r2 r1 r1 r1 r1 r1 r1 movrr r1, r2 register r1 register r2 none 1 move 1010 0111 kkkk kkkk mov a,#k a k none 1 110a aaaa aaaa aaaa jmp addr pc addr pc[13..16] unchange none 1 branch 111a aaaa aaaa aaaa call addr [top of stack] pc + 1 pc addr pc [13..16] unchange none 1 bank 1010 1110 0000 0kkk bank #k r4(rambs0) k (0~6) none 1 page 1010 1101 0000 000k page #k r5(pages) k (0~1) none 1
EM77950 bb controller 90 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 19 electrical specification 19.1 absolute maximum ratings temperature under bias 0 c to 70 c storage temperature -65 c to 150 c input voltage -0.3v to +3.6v output voltage -0.3v to +3.6v 19.2 dc electrical characteristic ta = 0 c ~ 70 c, vdd=3.3v 5%, vss=0v symbol parameter condition min typ max unit fxt crystal: vdd ~ 2.75v one cycle with one clock dc ? 48.0 mhz iil input leakage current for input pins vin = vdd, vss ? ? 2 a vih input high voltage port a ~ port f 0.8xvdd ? ? v vil input low voltage port a ~ port f vss ? 0.2xvdd v viht input high threshold voltage /rst 2.0 ? ? v vilt input low threshold voltage /rst ? ? 0.8 v vihx clock input high voltage osci, osco 2.5 ? ? v vilx clock input low voltage osci, osco ? ? 1.0 v voh1 output high voltage: pta, ptc, ptd, pte, ptf ioh = -8.0 ma 2.4 ? ? v voh2 output high voltage: ptb; rfio ioh = -8.0 ma 2.4 ? ? v vol1 output low voltage: pta, ptc, ptd, pte, ptf iol = 8.0 ma ? ? 0.4 v vol2 output low voltage: ptb; rfio iol = 8.0 ma ? ? 0.4 v iph pull-high current pull-high active, input pin at vss ? -6.5 ? a isb power down current all input and i/o pins at vdd, output pin floating, wdt enabled. ? ? 2 a isb power down current all input and i/o pins at vdd, output pin floating, wdt and all peripherals disabled. ? ? 1 a icc1 operating supply current (vdd = 3.3v) /reset = 'high', fosc = 32khz (rc type), output pin floating, wdt and all peripherals disabled. ? 60 ? a icc3 operating supply current (vdd = 3.3v) /reset= 'high', fosc = 6mhz (crystal type), output pin floating, and all peripherals disabled. ? 5 ? ma
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 91 (this specification is subject to change without further notice) 19.3 voltage detector electrical characteristic ta=25 c symbol parameter condition min typ max unit vdet detect voltage ? 1.8 2.0 2.2 v vrel release voltage ? ? vdet 1.05 ? v iss current consumption vdd = 3v ? ? 0.8 a vop operating voltage ? 0.7 * ? 3.5 v vdet/ ta vdet temperature characteristic 0 c ta 70 c ? ? -2 mv/ c * when the vdd voltage rises between vop=0.7v and vdet, the voltage detector output must be "low". 19.4 ac electrical characteristic 19.4.1 mcu ta = 0 c ~ 70 c, vdd=3.3 v 5%, vss=0v ta=0 c ~ 70 c, vdd=3.3 v 5%, vss=0v symbol parameter conditions min typ max unit dclk input clk duty cycle ? 45 50 55 % tins instruction cycle time (clks="0") crystal type rc type 125 500 ? dc dc ns ns ttcc tcc input period ? (tins+20)/n * ? ? ns tdrh device reset hold time ta = 25 c 9 18 30 ms trst /reset pulse width ta = 25 c 2000 ? ? ns twdt watchdog timer period ta = 25 c 9 18 30 ms tset input pin setup time ? ? 0 ? ms thold input pin hold time ? ? 20 ? ms tdelay output pin delay time cload=20pf ? 50 ? ms * n= selected prescaler ratio.
EM77950 bb controller 92 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) 19.4.2 bb ta=0 c ~ 70 c, vdd=3.3 v 5%, vss=0v symbol parameter min max unit 1/tosc oscillator frequency 0.1 24 mhz trdpw rd pulse width 3 * tosc+ ? ns tcsrd cs low to rd low tosc ? ns tadrd address valid for rd low 0 ? ns trddv rd low to data valid ? 3 * tosc+ ns trhdt data float after rd. ? tosc ns tdhar data hold after rd 0 ? ns trhdt time between consecutive rd pulses 2 * tosc ? ns trdan address valid after rd low 3 * tosc+ ? ns >0 will be determined according to cell library simulation. the values above were determined according to behavioral simulations. they take into account only the bb digital state-machine. thus, such values are for reference only.
EM77950 bb controller product specification (v1.0) 10.09.2007 ? 93 (this specification is subject to change without further notice) 20 application circuit 1 2 3 4 56 a b c d 6 5 4 3 2 1 d c b a title nu mber revisio n size b date: 20-aug-2003 sheet of fil e: d:\do cumen ts and sett ings\ admini strator\my do cumen ts \mcu_ lin e\keep d ata\d emo bo a drawn by : pf1 1 avdd 2 dvdd 3 pa0/kwu8 4 pa1/kwu9 5 pa2/kwua 6 pa3/kwub 7 /rst 8 pa4 9 pa5 10 pa6 11 pa 7/pwm 0 12 pb0/k wu 0 13 pb1/k wu 1 14 pb2/k wu 2 15 pb3/k wu 3 16 pb4/k wu 4 17 pb5/pw m 5 18 pb6/k wu 6 19 pb7/k wu 7 20 rf_act 21 tx rx 22 rfio 23 dv ss 24 pc0/sd i 25 pc2/sdo 27 pc3/int0 28 pc4/int1 29 pc5/pwm1 30 plcc 31 osco1 32 osci 33 avss 34 pd0/adc0 35 pd1/adc1 36 pd2/adc2 37 pd 3/adc3 38 pd 4/adc4 39 pd 5/adc5 40 pd 6/adc6 41 pd 7/adc7 42 vref 43 pe 0/adc8 44 pe 1/adc9 45 pe 2/adca 46 pe 3/adcb 47 pe 4/adcc 48 pe 5/adcd 49 pe 6/adce 50 pe 7/adcf 51 pc1/sd o 26 pf0/o sco2 52 et44 r510 v_ in 2 v_ out 1 gn d 3 tr1 apl58 83 +c1 1u f +c2 10 uf c3 100nf pwr_vcc vcc r1 r vcc r2 2.2m r3 22m tr1 8051 tr2 8051 r4 r lo w power vcc r9 1m 1 2 cn2 s_mtr c4 10 0n f d1 d4 14 8 mtr_vcc tr5 8051 r10 100k r11 1k sw1 sele ct sw2 start sw3 analog lo w power 1 2 3 4 5 6 cn7 rf module connector tx/rx rssi rfio rf_act gnd vcc 1 2 cn2 s_mtr mtr_vcc tr4 8051 r12 100k r13 1k d2 d4 14 8 c5 100nf y1 6mhz r14 1m c8 22pf c9 0. 1 c7 22 pf joy stick right2 rv2b jo y stick right1 rv2c vcc vcc rv2 jo ystick ri ght r21 24k r19 24k r17 24k r15 24k r22 1. 5k r20 1. 5k r18 1. 5k r16 1. 5k r33 24k r31 24k r29 24k r27 24 k r34 1k5 r32 1k5 r30 1k5 r28 1k 5 vcc 1 2 3 cn2 r24 1k 5 r23 1k 5 1 2 3 cn1 r26 1k5 r25 1k 5 vcc vcc vcc vcc jo y sti ck left2 rv1b jo y s ti ck le ft 1 rv1c vcc vcc rv1 jo ystick_ left mtr_vcc c11 10 0n f vcc jp1 1 2 3 4 8 7 6 5 sw1 sw dip c? 0.1 jsr_bl jsr_br jsr_bl jsr_br 10uf c24 10uf c25 c26 1uf 220nh l1 r7 1r vcc et44 r510 wireless joystick demo EM77950 formatted: font: 3 pt, font color: dark blue
EM77950 bb controller 94 ? product specification (v1.0) 10.09.2007 (this specification is subject to change without further notice) appendix a package type et no package type pin count package size EM77950a qfp52 52 14 20mm EM77950b qfp44 44 10 10mm b package information

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